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?2008 silicon storage technology, inc. s71323-03-000 07/08 1 the sst logo, superflash, and flashflex are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specification features: ? 8-bit 8051-compatible microcontroller (mcu) with embedded superflash memory ? fully software compatible ? development toolset compatible ? pin-for-pin package compatible ? sst89c58rc operation ? 0 to 40 mhz at 2.7-5.5v ? 34 kbyte single block superflash eeprom with two partitions ? 32 kbyte primary partition + 2 kbyte secondary partition ? flash block is divided into four application pages (8 kbyte) and one loader page (2 kbyte) ? individual page security lock ? address up to 64kb for external data memory ? in-system programming (isp) ? in-application programming (iap) ? small-sector architecture: 128-byte sector size ? total 1kbyte on-chip ram ? supports external address range up to 64 kbyte of program and data memory ? dual enhanced smbus ? up to 400 kbit per second ? full-duplex, enhanced uart ? framing error detection ? automatic address recognition ? brown-out reset (bor) ? nine interrupt sources at 4 priority levels ? three 16-bit timers/counters ? programmable watchdog timer (wdt) ? second dptr register ? four 8-bit i/o ports (32 i/o pins) ? i/o pins are 5v tolerant (pulled up and driven to 5.5v) ? standard 12 clocks per cycle, the device has an option to double the speed to 6 clocks per cycle ? speeds up to 40 mhz with 12 clock cycles per machine cycle ? speeds up to 20 mhz with 6 clock cycles per machine cycle - equivalent to 40 mhz ? enhanced hook emulation ? low power modes ? power-down mode with external interrupt wake-up ? idle mode ? temperature ranges: ? industrial (-40c to +85c) ? packages available ? 44-lead plcc ? 44-lead tqfp ? 40-contact wqfn ? all non-pb (lead-free) devices are rohs compliant product description the sst89c58rc is a member of the flashflex family of 8-bit micro controllers designed and manufactured with sst patented and proprietary superflash cmos semi- conductor process technology. the split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for customers. it uses the 8051 instruc- tion set and is pin-for-pin compatible with standard 8051 micro controller devices. with two enhanced smbus interfaces, the sst89c58rc supports speeds up to 400 kbps. it comes with 34 kbyte of on-chip flash eeprom program memory which is divided into two independent program memory partitions. the pri- mary partition occupies 32 kbyte of internal program mem- ory space and the secondary partition occupies 2 kbyte of internal program memory space. the flash memory can be programmed via a standard 87c5x otp eprom programmer fitted with a special adapter and firmware for sst devices. the sst89c58rc is designed to be programmed in-system on the printed cir- cuit board for maximum flexibility. it is pre-programmed with an example of the bootstrap loader in memory, demonstrat- ing initial user program code loading or subsequent user code updating via an isp operation. the sample bootstrap loader is for the user?s reference only, and sst does not guarantee its functionality. chip-erase operations will erase the pre-programmed sample code. in addition to 34 kbyte of superflash eeprom on-chip program memory and 1024 x8 bits of on-chip ram, the device can address up to 64 kbyte of external program memory and up to 64 kbyte of external ram. the highly-reliable, patented sst superflash technology and memory cell architecture offer a number of important advantages for designing and manufacturing flash eeproms. these advantages translate into significant cost and reliability benefits for customers. flashflex mcu sst89c58rc sst89e/ve5xc flashflex51 mcu
2 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 table of contents features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 i/o descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.0 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 program flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 data ram memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 expanded data ram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 in-application programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 in-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.0 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 timer set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3 programmable clock-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.0 serial i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 full-duplex, enhanced uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 enhanced smbus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3 timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.4 smbus sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.0 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.1 watchdog timer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.2 pure timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.3 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.4 feed sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.5 power saving considerations for using the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.0 security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.1 chip-level security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2 page-level security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 read operation under lock condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2 interrupt priority and polling sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
preliminary specification flashflex mcu sst89c58rc 3 ?2008 silicon storage technology, inc. s71323-03-000 07/08 10.0 power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.0 system clock and clock options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.1 clock input options and recommended ca pacitor values for oscillator . . . . . . . . . . . . . . . . . . . . . . 63 11.2 clock doubling option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.0 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.2 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.0 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.0 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 list of figures figure 1-1: functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2-1: pin assignments for 44-lead tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2-2: pin assignments for 44-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2-3: pin assignments for 40-contact wqfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3-1: program memory organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3-2: internal and external data memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figure 3-3: dual data pointer organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4-1: chip-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4-2: partition0-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 4-3: sector-erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 4-4: byte-program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 4-5: byte-verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 4-6: secure-page0-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 4-7: enable-clock-double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 4-8: boot sequence flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 4-9: hardware enter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6-1: framing error block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6-2: uart timings in mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6-3: uart timings in modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6-4: typical smbus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6-5: data transfer on the subus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6-6: smbus serial interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 7-1: block diagram of programmable watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 9-1: power-on reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 9-2: interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 11-1: oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 12-1: external program memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 figure 12-2: external data memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 12-3: external data memory write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 12-4: shift register mode timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 12-5: ac testing input/output test waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 12-6: float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 12-7: a test load example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 12-8: i dd test condition, active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 12-9: i dd test condition, idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 12-10: i dd test condition, power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 14-1: 44-lead plastic lead chip carrier (plcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 14-2: 44-lead thin quad flat pack (tqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 14-3: 40-contact very-very-thin quad flat no-lead (wqfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
preliminary specification flashflex mcu sst89c58rc 5 ?2008 silicon storage technology, inc. s71323-03-000 07/08 list of tables table 2-1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3-1: external data memory rd#, wr# with extram bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3-2: flashflex sfr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-3: cpu related sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-4: flash memory programming sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3-5: watchdog timer sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3-6: timer/counter sfr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3-7: interface sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3-8: feed sequence sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3-9: clock option sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4-1: product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 4-2: iap commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 4-3: command sequence table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 4-4: default boot vector settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5-1: timer/counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5-2: timer/counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5-3: timer/counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6-1: smbus sfr functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6-2: master transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 6-3: master receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6-4: slave receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 6-5: slave transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6-6: miscellaneous status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6-7: bit rate configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 9-1: interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 10-1: power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 11-1: recommended values for c1 and c2 by crystal type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 11-2: clock doubling features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 12-1: operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 12-2: reliability ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 12-3: ac conditions of test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 12-4: recommended system power-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 12-5: pin impedance (vdd=3.3v, ta=25 c, f=1 mhz, other pins open) . . . . . . . . . . . . . . . . . . . 65 table 12-6: dc characterist ics for sst89c58rc: t a = -40c to +85c; v dd = 2.7-5.5v; v ss = 0v. . . . 66 table 12-7: ac electrical characteristics t a = -40c to +85c, 2.7-5.5v@40mhz, v ss = 0v . . . . . . . . 67 table 12-8: serial port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 12-9: flash memory programming/verification parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 14-1: revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 1.0 functional blocks figure 1-1: functional block diagram 9 interrupts superflash eeprom primary partition 32k x8 secondary partition 2k x8 i/o i/o i/o i/o watchdog timer interrupt control 8051 cpu core ram 1k x8 security lock i/o port 0 i/o port 1 i/o port 2 i/o port 3 8-bit enhanced uart bor timer 0 (16-bit) timer 1 (16-bit) timer 2 (16-bit) 8 8 8 8 1323 b1.0 enhanced smbus 0 flash control unit 8 oscillator enhanced smbus 1 alu, acc, b-register, instruction register, program counter, timing and control
preliminary specification flashflex mcu sst89c58rc 7 ?2008 silicon storage technology, inc. s71323-03-000 07/08 2.0 pin assignments figure 2-1: pin assignments for 44-lead tqfp figure 2-2: pin assignments for 44-lead plcc (sda1) p1.5 (sda0) p1.6 (scl0) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 ( t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# nc ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 (scl1) p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) nc v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 1323 44-tqfp tqj p1.0 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 44-lead tqfp top view 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 (sda1) p1.5 (sda0) p1.6 (scl0) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# nc ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 p1.4 (scl1) p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) nc v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 44-lead plcc top view 1323 44-plcc nj p2.0
8 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 2-3: pin assignments for 40-contact wqfn 1323 40-wqfn qi p3.0 (sda1) p1.5 (sda0) p1.6 (scl0) p1.7 rst (rxd) p3.0 (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 1 40 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 (scl1) p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) top view (contacts facing down)
preliminary specification flashflex mcu sst89c58rc 9 ?2008 silicon storage technology, inc. s71323-03-000 07/08 2.1 pin descriptions table 2-1: pin descriptions (1 of 2) symbol type 1 name and functions p0[7:0] i/o port 0: port 0 is an 8-bit open drain bi-directional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins that have ?1?s written to them float, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. in this application, it uses strong internal pull-ups when transitioning to ?1?s. external pull-ups are required as a general purpose i/o port. p1[7:0] i/o with internal pull-up port 1: port 1 is an 8-bit bi-directional i/o port with internal pull-ups. the port 1 output buffers can drive ls ttl inputs. port 1 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. p1[0] i/o t2: external count input to timer/counter 2 or clock-out from timer/counter 2 p1[1] i t2ex: timer/counter 2 capture/reload trigger and direction control p1[2] i/o gpio p1[3] i/o gpio p1[4] i/o scl1: smbus1 serial clock input / output p1[5] i/o sda1: smbus1 serial data input / output p1[6] i/o sda0: smbus0 serial data input / output p1[7] i/o scl0: smbus1 serial clock input / output p2[7:0] i/o with internal pull-up port 2: port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when ?1?s are written to t hem and can be used as inputs in this state. as inputs, port 2 pins that are externally pulled low will source current because of the internal pull- ups. port 2 sends the high-order address byte duri ng accesses to external data memory that use 16-bit address (movx@dptr). in this application, it uses strong internal pull-ups when transi- tioning to v oh . p3[7:0] i/o with internal pull-up port 3: port 3 is an 8-bit bi-directional i/o port with internal pull-ups. the port 3 output buffers can drive ls ttl inputs. port 3 pins are pulled high by the internal pull-ups when ?1?s are written to them and can be used as inputs in this state. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. p3[0] i rxd: universal asynchronous receiver/transmitter (uart) - receive input p3[1] o txd: uart - transmit output p3[2] i int0#: external interrupt 0 input p3[3] i int1#: external interrupt 1 input p3[4] i t0: external count input to timer/counter 0 p3[5] i t1: external count input to timer/counter 1 p3[6] o wr#: external data memory write strobe p3[7] o rd#: external data memory read strobe psen# i/o program store enable: psen# is the read strobe to external program. when the device is exe- cuting from internal program memory, psen# is inactive (v oh ). rst i reset: while the oscillator is runni ng, a ?high? logic state on this pin for two machine cycles will reset the device. ea# i external access enable: ea# must be connected to v ss in order to enable the device to fetch code from the external program memory. ea# must be strapped to v dd for internal program exe- cution. however, disable-extern-boot (see sect ion 8.0, ?security lock?) will disable ea#, and program execution is only possible from internal program memory.
10 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 2.2 i/o descriptions the device supports 2.7~5.5v supply, and the i/o pins are 5v tolerant. however, applying any voltage beyond power supply in quai-bidirectional mode is not recommended because doing so causes current to flow from the pin to vdd which consumes extra power. ale/prog# i/o address latch enable: ale is the output signal for latching the low byte of the address during an access to external memory. this pin is also the programming pulse input (prog#) for flash programming. normally the ale 2 is emitted at a constant ra te of 1/6 the crystal frequency 3 . one ale pulse is skipped during each access to external data memory. however, if ao is set to ?1?, ale is disabled. nc i/o no connect xtal1 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator cir- cuits. xtal2 o crystal 2: output from the inverting oscillator amplifier. v dd i power supply v ss i ground t2-1.0 1323 1. i = input; o = output 2.ale loading issue: when ale pin experienc es higher loading (>30pf) during the reset, the mcu may accidentally enter into mode s other than normal working mode. the solution is to add a pull-up resistor of 3-50 k to v dd , e.g. for ale pin. 3. for 6 clock mode, ale is emitted at 1/3 of crystal frequency. table 2-1: pin descriptions (continued) (2 of 2) symbol type 1 name and functions
preliminary specification flashflex mcu sst89c58rc 11 ?2008 silicon storage technology, inc. s71323-03-000 07/08 3.0 memory organization the sst89c58rc has separate address spaces for pro- gram and data memory. 3.1 program flash memory there are two internal flash memory partitions in the device. the primary flash memory partition (partition 0) has 32 kbyte. the secondary flash memory partition (partition 1) has 2 kbyte. the 32 kbyte primary flash partition is organized as 256 sectors, each sector consists of 128 bytes. the primary partition is divided into four logical pages as shown in figure 3-1. the 2k x8 secondary flash partition is organized as 16 sec- tors, each sector consists also of 128 bytes. for both partitions, the 7 least significant program address bits select the byte within the sector. the remainder of the program address bits select the sector within the partition. enboot bit in auxr1 (a2h) determines whether the sec- ond partition (loader page) is enabled or disabled. if enboot is clear (default), the secondary partition (parti- tion 1) is disabled. enboot is automatically set when either of the following occur: the ?boot-from-zero? bit is non-zero during reset or when p1.0 and p1.1 are pulled low while ea# is simultaneously held high on the falling edge of the reset. if user-code boots from the default boot vector (0xf800) or from the user boot vector. the enboot is set by hard- ware automatically to enable secondary partition (partition 1). figure 3-1: program memory organization 1323 f01.0 (8 kbyte) app. page 30 kbyte external memory logical address mapping 64 kbyte external memory ea# = 0 ffffh 0000h ea# = 1 ea# = 1 ffffh 0000h 8000h 7fffh 32 kbyte external memory ffffh 0000h (2 kbyte) loader page enboot disabled enboot enabled 0xf800h 0xf7ffh (8 kbyte) app. page (8 kbyte) app. page (8 kbyte) app. page (8 kbyte) app. page (8 kbyte) app. page (8 kbyte) app. page (8 kbyte) app. page 8000h 7fffh 32 kbyte partition 0 32 kbyte partition 0 2 kbyte partition 1
12 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 3.2 data ram memory the data ram has 1kbyte of internal memory. the first 256 bytes are available by default. the second 256 bytes are enabled by clearing the extram bit in the auxr reg- ister. the ram can be addressed up to 64 kbyte for exter- nal data memory. 3.3 expanded data ram addressing the sst89c58rc has the capability of 1 kbyte of ram. see figure 3-2. the device has four sections of internal data memory: 1. the lower 128 bytes of ram (00h to 7fh) are directly and indirectly addressable. 2. the higher 128 bytes of ram (80h to ffh) are indirectly addressable. 3. the special function registers (80h to ffh) are directly addressable only. 4. the expanded ram of 768 bytes (00h to 2ffh) is indirectly addressable by the move external instruction (movx) and clearing the extram bit. (see ?auxiliary register (auxr)? in section 3.5, ?special function registers?) since the upper 128 bytes occupy the same addresses as the sfrs, the ram must be accessed indirectly. the ram and sfrs space are physically separate even though they have the same addresses. when instructions access addresses in the upper 128 bytes (above 7fh), the mcu determines whether to access the sfrs or ram by the type of instruction given. if it is indirect, then ram is accessed. if it is direct, then an sfr is accessed. see the examples below. indirect access: mov @r0, #data ; r0 contains 90h register r0 points to 90h which is located in the upper address range. data in ?#data? is written to ram location 90h rather than port 1. direct access: mov 90h, #data ; write data to p1 data in ?#data? is written to port 1. instructions that write directly to the address write to the sfrs. to access the expanded ram, the extram bit must be cleared and movx instructions must be used. the extra 768 bytes of memory is physically located on the chip and logically occupies the first 768 bytes of external memory (addresses 000h to 2ffh). when extram = 0, the expanded ram is indirectly addressed using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. accessing the expanded ram does not affect ports p0, p3.6 (wr#), p3.7 (rd#), or p2. with extram = 0, the expanded ram can be accessed as in the following example. expanded ram access (indirect addressing only): movx @dptr, a ; dptr contains 0a0h dptr points to 0a0h and data in ?a? is written to address 0a0h of the expanded ram rather than external memory. access to external memory higher than 2ffh using the movx instruction will access external memory (0300h to ffffh) and will perform in the same way as the standard 8051, with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. when extram = 1, movx @ri and movx @dptr will be similar to the standard 8051. using movx @ri pro- vides an 8-bit address with multiplexed data on port 0. other output port pins can be used to output higher order address bits. this provides external paging capabilities. using movx @dptr generates a 16-bit address. this allows external addressing up the 64k. port 2 provides the high-order eight address bits (dph), and port 0 multiplexes the low order eight address bits (dpl) with data. both movx @ri and movx @dptr generates the necessary read and write signals (p3.6 - wr# and p3.7 - rd#) for external memory use. table 3-1 shows external data mem- ory rd#, wr# operation with extram bit. the stack pointer (sp) can be located anywhere within the 256 bytes of internal ram (lower 128 bytes and upper 128 bytes). the stack pointer may not be located in any part of the expanded ram.
preliminary specification flashflex mcu sst89c58rc 13 ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 3-2: internal and external data memory structure table 3-1: external data memo ry rd#, wr# with extram bit movx @dptr, a or movx a, @dptr movx @ri, a or movx a, @ri auxr addr < 0300h addr >= 0300h addr = any extram = 0 rd# / wr# not asserted rd# / wr# asserted rd# / wr# not asserted 1 extram = 1 rd# / wr# asserted rd# / wr# asserted rd# / wr# asserted t3-1.0 1323 1. access limited to eram address within 0 to 0ffh. 100h to 02ffh is not accessible. 000h 2ffh 00h ffh upper 128 bytes internal ram lower 128 bytes internal ram (indirect & direct addressing) (indirect addressing) (direct addressing) special function registers (sfrs) 80h ffh ffffh 000h external data memory 2ffh 0000h external data memory extram = 0 extram = 1 expanded ram 0300h (indirect addressing) ffffh (indirect addressing) (indirect addressing) 80h 7fh 1294 f02.0 expanded ram 768 bytes
14 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 3.4 dual data pointers the sst89c58rc has two 16-bit data pointers. the dptr select (dps) bit in auxr1 determines which of the two data pointers is accessed. when dps=0, dptr0 is selected; when dps=1, dptr1 is selected. quickly switching between the two data pointers can be accom- plished by a single inc instruction on auxr1. (see figure 3-3) 3.5 special function registers most of the unique features of the flashflex micro control- ler family are controlled by bits in special function registers (sfrs) located in the sfr memory map shown in table 3- 2. individual descriptions of each sfr are provided and reset values indicated in tables 3-3 to 3-7. figure 3-3: dual data pointer organization dpl 82h external data memory dps 1323 f03.0 dph 83h dptr0 dptr1 auxr1 / bit0 dps = 0 dptr0 dps = 1 dptr1
preliminary specification flashflex mcu sst89c58rc 15 ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 3-2: flashflex sfr memory map 8 bytes f8h ffh f0h b f7h e8h ien1 efh e0h acc e7h d8h sm0con0 sm0sta sm0dat sm0adr sm0sclh sm0scll sm0con1 dfh d0h psw sm1con0 sm1sta sm1dat sm1adr sm1sclh sm1scll sm1con1 d7h c8h t2con t2mod rcap2l rcap2h tl2 th2 cfh c0h wdtc sfis1 c7h b8h ip0 s0aden cosr bfh b0h p3 sfcf sfcm sfal sfah sfdt sfst ip0h b7h a8h ien0 saddr afh a0h p2 pmc auxr1 a7h 98h s0con s0buf 9fh 90h p1 ip1 ip1h sfiso 97h 88h tcon tmod tl0 tl1 th0 th1 auxr 8fh 80h p0 sp dpl dph wdtd pcon 87h t3-2.0 1323 table 3-3: cpu related sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb acc 1 accumulator e0h acc[7:0] 00h b 1 b register f0h b[7:0] 00h psw 1 program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 82h dpl[7:0] 00h dph data pointer high 83h dph[7:0] 00h ien0 1 interrupt enable a8h ea et2 es et1 ex1 et0 ex0 00h ien1 1 interrupt enable a e8h - ewd - - - - em1 em0 x0xxxx00b ip0 interrupt priority reg b8h - - pt2 ps0 pt1 px1 pt0 px0 xx000000b ip0h interrupt priority reg high b7h - - pt2h ps0h pt1h px1h pt0h px0h xx000000b ip1 interrupt priority reg a 91h - pwd - - - - pm1 pm0 x0xxxx00b ip1h interrupt priority reg a high 92h - pwdh - - - - pm1h pm0h x0xxxx00b pcon power control 87h smod1 smod0 - pof gf1 gf0 pd idl 00x10000b auxr auxiliary reg 8eh - - - - - - extram ao xxxxxxx10b auxr1 auxiliary reg 1 a2h - - enboot - gf2 0 - dps xx1x00x0b pmc power manage- ment control a1h - - wdu tct tct2 smb0 smb1 uart xx000000b t3-3.0 1323
16 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 1. bit addressable sfrs table 3-4: flash memory programming sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sfcf superflash configuration b1h cmd_statu s iapen - hwiap - sfst_sel 01x0x000b sfcm superflash command b2h - sfcm[6:0] x0000000b sfal superflash address low b3h superflash low order byte address register a 7 to a 0 (sfal) 00h sfah superflash address high b4h superflash high order byte address register a 15 to a 8 (sfah) 00h sfdt superflash data b5h superflash data register 00h sfst superflash status b6h sfst_sel= 0h manufacturer?s id bfh sfst_sel= 1h device id0 (f7h indicates device id1 is real id) sfst_sel= 2h device id1 sfst_sel= 3h boot vector sfst_sel= 4h - - - page4 page3 page2 page1 page0 xxx11111b sfst_sel= 5h x boot from zero boot- from- user- vector enable clock- double disable- extern- host- cmd disable- extern- movc disable- extern- boot disable- extern- iap x1111111b t3-4.0 1323 table 3-5: watchdog timer sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb wdtc watchdog timer control c0h - wdton wdfe - wdre wdts wdt swdt x00x0000b wdtd watchdog timer data/reload 85h watchdog timer data/reload 00h t3-5.0 1323
preliminary specification flashflex mcu sst89c58rc 17 ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 3-6: timer/counter sfr symbol description direct address bit address, symbol, or alternative port function reset value msb lsb tmod timer/counter mode control 89h timer 1 timer 0 00h gate c/t# m1 m0 gate c/t# m1 m0 tcon 1 timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 msb 8ch th0[7:0] 00h tl0 timer 0 lsb 8ah tl0[7:0] 00h th1 timer 1 msb 8dh th1[7:0] 00h tl1 timer 1 lsb 8bh tl1[7:0] 00h t2con 1 timer/counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h t2mod# timer 2 mode control c9h - - - - - - t2oe dcen xxxxxx00b th2 timer 2 msb cdh th2[7:0] 00h tl2 timer 2 lsb cch tl2[7:0] 00h rcap2h timer 2 capture msb cbh rcap2h[7:0] 00h rcap2l timer 2 capture lsb cah rcap2l[7:0] 00h t3-6.0 1323 1. bit addressable sfrs
18 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 3-7: interface sfrs symbol description direct address bit address, symbol, or al ternative port function reset value msb lsb s0buf serial data buffer 99h sbuf[7:0] indeter minate s0con serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h s0addr slave address a9h s0addr[7:0] 00h s0aden slave address mask b9h s0aden[7:0] 00h sm0con0 smbus0 contol0 d9h smben_0 sta_0 sto_0 si_0 aa_0 fte_0 toe_0 crsel_0 00h sm0sta smbus0 status dah sm0sta[7:3] 0 0 0 f8h sm0dat smbus0 data dbh sm0dat[7:0] 00h sm0adr smbus0 address dch sm0 slave address[6:0] gc_0 00h sm0sclh smbus0 scl high duty ddh sm0sclh[7:0] 00h sm0scll smbus0 scl lowduty deh sm0scll[7:0] 00h sm0con1 smbus0 contol1 dfh 1 1 1 1 pwru p_si0 pwr up_e n0 stady _0 exhold_0 f0h sm1con0 smbus1 contol0 d1h smben_1 sta_1 sto_1 si_1 aa_1 fte_1 toe_1 crsel_1 00h sm1sta smbus1 status d2h sm1sta[7:3] 0 0 0 f8h sm1dat smbus1 data d3h sm1dat[7:0] 00h sm1adr smbus1 address d4h sm1 slave address sm1adr[7:1] gc_1 00h sm1sclh smbus1 scl high duty d5h sm1sclh[7:0] 00h sm1scll smbus1 scl lowduty d6h sm1scll[7:0] 00h sm1con1 smbus1 contol1 d7h 1 1 1 1 pwru p_si1 pwr up_e n1 stady _0 exhold_0 foh p0 1 port 0 80h p0[7:0] ffh p1 1 port 1 90h - - - - - - t2ex t2 ffh p2 1 port 2 a0h p0[7:0] ffh p3 1 port 3 b0h rd# wr# t1 t0 int1# int0# txd rxd ffh t3-7.1 1323 1. bit addressable sfrs table 3-8: feed sequence sfrs symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sfis0 sequence reg 0 97h (write only) 00h sfis1 sequence reg 1 c4h (write only) 00h t3-8.0 1323 table 3-9: clock option sfr symbol description direct address bit address, symbol, or alternative port function reset value msb lsb cosr clock option register bfh - - - - coen co_rel co_in 0x00000b t3-9.0 1323
preliminary specification flashflex mcu sst89c58rc 19 ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function cmd_status iap command completion status 0: iap command is ignored 1: iap command is completed fully iapen iap enable bit 0: disable all iap commands (commands will be ignored) 1: enable all iap commands hwiap boot status flag 0: system boots up without special pin configuration setup 1:system boots up with both p1[0] and p1[1] pins in logic low state curing reset sfst_sel provide index to read back information when read to sfst register is executed (see , ?superflash status register (sfst) (read only register)? on page 21 for detailed settings) superflash configuration register (sfcf) location76543210reset value b1h cmd_ status iapen - hwiap - sfst_sel 01x0x000b
20 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function - reserved fcm[6:0] flash operation command 000_0001b chip-erase 000_1011b sector-erase 000_1101b partition0-erase 000_1100b byte-verify 000_1110b byte-program 000_0011b secure-page page-level security commands sfah=90h; secure-page0 sfah=91h; secure-page1 sfah=92h; secure-page2 sfah=93h; secure-page3 sfah=94h; secure-page4 000-0101b secure-chip chip-level security commands sfah=b0h; disable-extern-iap sfah=b1h; disable-extern-boot sfah=b2h; disable-extern-movc sfah=b3h; disable-extern-host-cmd 000-1000b boot options boot option setting commands sfah=e0h; enable-clock-double sfah=e1h; prog-boot-from-user-vector sfah=e2h; prog-boot-jumper 000-1001b set-user-boot-vector all other combinations are not implemented, and reserved for future use. symbol function sfal mailbox register for interfacing with flash memory block. (low order address register) symbol function sfah mailbox register for interfacing with flash memory block. (high order address register) superflash command register (sfcm) location76543210reset value b2h - fcm6 fcm5 fcm4 fcm3 fcm2 fcm1 fcm0 x0000000b superflash address registers (sfal) location76543210reset value b3h superflash low order byte address register 00h superflash address registers (sfah) location76543210reset value b4h superflash high order byte address register 00h
preliminary specification flashflex mcu sst89c58rc 21 ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function sfdt mailbox register for interfacing with flash memory block. (data register) symbol function sfst this is a read-only register. the read-back value is indexed by sfst_sel in the superflash configurat ion register (sfcf) sfst_sel=0h: manufacturer?s id 1h: device id0 = f7h 2h: device id1 = device id (refer to table 4-1 on page 33) 3h: boot vector 4h: page-security bit setting 5h: chip-level security bit setting and boot options symbol function ea global interrupt enable 0 = disable 1 = enable et2 timer 2 interrupt enable es0 serial interrupt enable et1 timer 1 interrupt enable ex1 external 1 interrupt enable et0 timer 0 interrupt enable ex0 external 0 interrupt enable symbol function ewd watchdog interrupt enable 0 = disable 1 = enable em1 smbus 1 interrupt enable em0 smbus 0 interrupt enable superflash data register (sfdt) location76543210reset value b5h superflash data register 00h superflash status register (sfst) (read only register) location76543 2 10reset value b6h superflash status register 1011 1111b interrupt enable (ien0) location76543210reset value a8h ea - et2 es0 et1 ex1 et0 ex0 0x000000b interrupt enable a (ien1) location76543210reset value e8h-ewd----em1em0x0 xxxx00b
22 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function pt2 timer 2 interrupt priority bit ps0 serial port interrupt priority bit pt1 timer 1 interrupt priority bit px1 external interrupt 1 priority bit pt0 timer 0 interrupt priority bit px0 external interrupt 0 priority bit symbol function pt2h timer 2 interrupt priority bit high ps0h serial port interrupt priority bit high pt1h timer 1 interrupt priority bit high px1h external interrupt 1 priority bit high pt0h timer 0 interrupt priority bit high px0h external interrupt 0 priority bit high symbol function pwd watchdog interrupt priority bit pm1 smbus 1 interrupt priority bit pm0 smbus 0 interrupt priority bit symbol function pwdh watchdog interrupt priority bit high pm1h smbus 1 interrupt priority bit high pm0h smbus 0 interrupt priority bit high interrupt priority (ip0) location76543210reset value b8h - - pt2 ps0 pt1 px1 pt0 px0 xx000000b interrupt priority high (ip0h) location76543210reset value b7h - - pt2h ps0h pt1h px1h pt0h px0h xx000000b interrupt priority (ip1) location76543210reset value 91h-pwd----pm1pm0x0 xxxx00b interrupt priority high (ip1h) location76543210reset value 92h-pwdh----pm1hpm0hx0 xxx00b
preliminary specification flashflex mcu sst89c58rc 23 ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function extram internal/external ram access 0: internal expanded ram access within range of 00h to ffh using movx @ri / @dptr. beyond 100h, the mcu always accesses external data memory for details, refer to section 3.3, ?expanded data ram addressing? 1: external data memory access ao disable/enable ale 0: ale is emitted at a consta nt rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 f osc in 12 clock mode 1: ale is active only during a movx or movc instruction symbol function enboot enable partition 1 gf2 general purpose user-defined flag dps dptr registers select bit 0: dptr0 is selected 1: dptr1 is selected symbol function sfis0 register used with sfis1 to provide a feed sequence to validate writing to wdtc and sfcm. without a proper feed sequence, writing to sfcm will be ignored and writing to wdtc in watchdog mode will caus e an immediate watchdog reset. symbol function sfis1 register used with sfis0 to provide a feed sequence to validate writing to wdtc and sfcm. auxiliary register (auxr) location76543210reset value 8eh------extramao xxxxxx10b auxiliary register 1 (auxr1) location76543210reset value a2h - - enboot - gf2 0 - dps xx1x00x0b sequence register 0 (sfis0) location76543210reset value 97h (write only) n/a sequence register 1 (sfis1) location76543210reset value c4h (write only) n/a
24 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function wdton watchdog timer start control bit (used in watchdog mode) 0: watchdog timer can be started or stopped freely during watchdog mode. 1: start watchdog timer; bit cannot be cleared by software. wdfe watchdog feed sequence error flag 0: watchdog feed sequence error has not occurred. 1: due to an incorrect feed sequence before writing to wdtc in watchdog mode, the hardware entered watchdog reset and set this flag to ?1?. this is for software to detect whether the watchdog reset was caused by timer expiration or an incorrect feed sequence. wdre watchdog timer reset enable. 0: disable watchdog timer reset. 1: enable watchdog timer reset. wdts watchdog timer reset flag. 0: external hardware reset or power-on reset clears the flag. flag can also be cleared by writing a 1. flag survives if chip reset happened because of watchdog timer overflow. 1: hardware sets the flag on watchdog overflow. wdt watchdog timer refresh. 0: hardware resets the bit when refresh is done. 1: software sets the bit to force a watchdog timer refresh. swdt start watchdog timer. 0: stop wdt. 1: start wdt. watchdog timer control register (wdtc) location76543210reset value c0h - wdton wdfe - wdre wdts wdt swdt x00x0000b watchdog timer data/reload register (wdtd) location76543210reset value 85h watchdog timer data/reload 00h
preliminary specification flashflex mcu sst89c58rc 25 ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function coen clock divider enable 0: disable clock divider 1: enable clock divider co_sel clock divider selection 00b: 1/4 clock source 01b: 1/16 clock source 10b: 1/256 clock source 11b: 1/1024 clock source co_in clock source selection 0b: select clock from 1x clock 1b: select clock from 2x clock the default value of this bit is set during power-on reset by copying from enable_clock_double_i non-volatile bit setting. co_in can be changed during normal operation to select the double clock option. if the clock source is a 1x clock, the clock divider exports 1/4, 1/16, 1/256, or 1/1024 of the input clock. if the clock source is a 2x clock, the clock divider exports 1/2, 1/8, 1/128, or 1/512 of the input clock. symbol function wdu watchdog timer clock control 0:the clock for the watchdog timer is running 1:the clock for the watchdog timer is stopped tct timer 0/1 clock control 0:the timer 0/1 logic is running 1:the timer 0/1 logic is stopped tct2 timer 2 clock control 0:the timer 2 logic is running 1:the timer 2 logic is stopped smb0 smbus 0 clock control 0:the smbus0 logic is running 1:the smbus0 logic is stopped smb1 smbus 1 clock control 0:the smbus0 logic is running 1:the smbus0 logic is stopped uart uart clock control 0:the uart logic is running 1:the uart logic is stopped clock option register (cosr) location76543210reset value bfh---- coen co_sel co_in xxxx0000h power management control register (pmc) location76543210reset value a1h - - wdu tct tct2 smb0 smb1 uart xx000000b
26 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function smben_0 smbus enable 0: disable smbus 1: enable smbus sta_0 start flag 0: no start conditio n or repeated start condition will be generated 1: start or repeated star t condition will be generated sto_0 stop flag 0: no stop condition is generated 1: stop condition is generated si_0 serial interrupt flag 0: no serial interrupt is requested, no stretching on the scl 1: a serial interrupt is requested, the scl line is stretched (if ea and es1 are both set) aa_0 assert acknowledge flag -this bit defines the type of acknowledge returned during the acknowledge cycle on the scl line. 0: a ?not acknowledge? (high level on sda) is returned during the acknowledge cycle 1: an ?acknowledge? (low level on sda) is returned during the acknowledge cycle fte_0 bus free (scl high) timeout enable 0: bus free timeout disabled 1: bus free timeout enabled toe_0 scl low timeout enable 0: scl low timeout disabled 1: scl low timeout enabled crsel_0 scl clock source selection 0: smbus internal baud generator generates the scl 1: timer1 overflow generates the scl smbus0 control register0 (sm0con0) location76543210reset value d9h smben_0 sta_0 sto_0 si_0 aa_0 fte_0 toe_0 crsel_0 00h
preliminary specification flashflex mcu sst89c58rc 27 ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function pwrup_si0 power-down wakeup flag - when the subus wakes up the mcu, the flag bit is set by hardware. the bit is in ready-only mode. only writing ?0? to this bit will clear the flag. if smbus interrupt enable bit is set, then the smbus interrupt is generated when the flag bit is ?1?. 0: no wakeup flag 1: wakeup flag occurs pwrup_en0 power-down wakeup enable 0: smbus power-down wakeup function disabled 1: smbus power-down wakeup function enabled stady_0 start condition long delay enable 0: start condition long delay disabled 1: start condition long delay enabled exthold_0 external data hold time setting 0: sda hold time is 20 system clock periods 1: sda hold time is 3 system clock periods symbol function smben_1 smbus enable 0: disable smbus 1: enable smbus sta_1 start flag 0: no start conditio n or repeated start condition will be generated 1: start or repeated star t condition will be generated si_1 serial interrupt flag 0: no serial interrupt is requested, no stretching on the scl 1: a serial interrupt is requested, the scl line is stretched (if ea and es1 are both set) aa_1 assert acknowledge flag -this bit defines the type of acknowledge returned during the acknowledge cycle on the scl line. 0: a ?not acknowledge? (high level on sda) is returned during the acknowledge cycle 1: an ?acknowledge? (low level on sda) is returned during the acknowledge cycle fte_1 bus free (scl high) timeout enable 0: bus free timeout disabled 1: bus free timeout enabled toe_1 scl low timeout enable 0: scl low timeout disabled 1: scl low timeout enabled crsel_1 scl clock source selection 0: smbus internal baud generator generates the scl 1: timer1 overflow generates the scl smbus0 control register1 (sm0con1) location 7 6 5 4 3 2 1 0 reset value dfh 1 11 1 pwrup_si0 pwrup_en0 stady_0 exthold_0 f0h smbus1 control register0 (sm1con0) location76543210reset value d1h smben_1 sta_1 sto_1 si_1 aa_1 fte_1 toe_1 crsel_1 00h
28 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function pwrup_si1 power-down wakeup flag - when the subus wakes up the mcu, the flag bit is set by hardware. the bit is in ready-only mode. only writing ?0? to this bit will clear the flag. if smbus interrupt enable bit is set, then the smbus interrupt is generated when the flag bit is ?1?. 0: no wakeup flag 1: wakeup flag occurs pwrup_en1 power-down wakeup enable 0: smbus power-down wakeup function disabled 1: smbus power-down wakeup function enabled stady_1 start condition long delay enable 0: start condition long delay disabled 1: start condition long delay enabled exthold_1 external data hold time setting 0: sda hold time is 20 system clock periods 1: sda hold time is 3 system clock periods symbol function sm0sta this is a read-only sfr. the five most significant bits contain the status code. the three least significant bits are always ?0?. symbol function sm1sta this is a read-only sfr. the five most significant bits contain the status code. the three least significant bits are always ?0?. smbus1 control register1 (sm1con1) location 7 6 5 4 3 2 1 0 reset value d7h 1 11 1 pwrup_si1 pwrup_en1 stady_1 exthold_1 f0h smbus0 status register (sm0sta) location76543210reset value dah sm0sta[7:3] 0 0 0 f8h smbus1 status register (sm1sta) location76543210reset value d2h sm0sta[7:3] 0 0 0 f8h smbus0 data register (sm0dat) location76543210reset value dbh sm0dat[7:0] 00h smbus1 data register (sm1dat) location76543210reset value d3h sm1dat[7:0] 00h
preliminary specification flashflex mcu sst89c58rc 29 ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function sm0sclh[7:0] set the scl high duration symbol function sm0sclh[7:0] set the scl low duration symbol function sm0sclh[7:0] set the scl high duration symbol function sm0sclh[7:0] set the scl low duration smbus01 address register 0 (sm0adr) location76543210reset value d4h sm0 slave address [7:1] gc_0 00h smbus1 address register 1 (sm1adr) location76543210reset value d4h sm1 slave address [7:1] gc_1 00h smbus0 high-duty setting register (sm0sclh) location76543210reset value ddh sm0sclh[7:0] 00h smbus0 low-duty setting register (sm0scll) location76543210reset value deh sm0scll[7:0] 00h smbus1 high-duty setting register (sm1sclh) location76543210reset value d5h sm1sclh[7:0] 00h smbus1 low-duty setting register (sm1scll) location76543210reset value d6h sm0scll[7:0] 00h
30 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function smod1 double baud rate bit. if smod1 = 1, timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. smod0 fe/sm0 selection bit. 0: scon[7] = sm0 1: scon[7] = fe, pof power-on reset status bit, this bit will not be affected by any other reset. pof should be cleared by software. 0: no power-on reset. 1: power-on reset occurred gf1 general-purpose flag bit. gf0 general-purpose flag bit. pd power-down bit, this bit is cleared by hardware after exiting from power-down mode. 0: power-down mode is not activated. 1: activates power-down mode. idl idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: idle mode is not activated. 1: activates idle mode. power control register (pcon) location76543210reset value 87h smod1 smod0 - pof gf1 gf0 pd idl 00x10000b
preliminary specification flashflex mcu sst89c58rc 31 ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function fe set smod0 = 1 to access fe bit. 0: no framing error 1: framing error. set by receiver when an invalid stop bit is detected. this bit needs to be cleared by software. sm0 smod0 = 0 to access sm0 bit. serial port mode bit 0 sm1 serial port mode bit 1 sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then ri will not be set unless the re ceived 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then ri will not be activated unless a valid stop bit wa s received. in mode 0, sm2 should be 0. ren enables serial reception. 0: to disable reception. 1: to enable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission, must be cleared by software. ri receive interrupt flag. set by hardware at the end of the8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. serial port control register (s0con) location76543210reset value 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00000000b sm0 sm1 mode description baud rate 1 1. f osc = oscillator frequency 0 0 0 shift register f osc /6 (6 clock mode) or f osc /12 (12 clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 or f osc /16 (6 clock mode) or f osc /64 or f osc /32 (12 clock mode) 1 1 3 9-bit uart variable
32 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 symbol function tf2 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when ti mer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk transmit clock flag. when se t, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tc lk = 0 causes timer 1 overflow to be used for the transmit clock. exen2 timer 2 external enable flag. when set, allows a capture or rel oad to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 start/stop control for timer 2. a logic 1 starts the timer. c/t2# timer or counte r select (timer 2) 0: internal timer (osc/6 in 6 clock mode, osc/12 in 12 clock mode) 1: external event counter (falling edge triggered) cp/rl2# capture/reload flag. when set, captures will occur on ne gative transitions at t2ex if exen2 = 1. when cleared, aut o-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is fo rced to auto-reload on timer 2 overflow. symbol function - not implemented, reserved for future use. note: user should not write ?1?s to reserved bits. the value read from a rese rved bit is indeterminate. t2oe timer 2 output enable bit. dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down counter. timer/counter 2 control register (t2con) location76543210reset value c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h timer/counter 2 mode control (t2mod) location76543210reset value c9h------t2oedcen xxxxxx00b
preliminary specification flashflex mcu sst89c58rc 33 ?2008 silicon storage technology, inc. s71323-03-000 07/08 4.0 flash memory programming the device internal flash memory can be programmed or erased using in-application programming (iap). 4.1 product identification the read-id command accesses the signature bytes that identify the device and the manufacturer as sst. external programmers primarily use these signature bytes in the selection of programming algorithms. 4.2 in-application programming the iap/isp functions are issued via the sst mail box scheme. detailed flash block operations are performed by the flash control unit. while th e flash control executes iap commands, the cpu is on hold since there is only one physical flash block in the sst89c58rc devices. when iap commands finish, the cpu can resume execution of the application code. so the application code needs to turn off the interrupt or turn off the peripheral modules before it issues iap commands since the cpu cannot respond to the interrupt or poll the sfr status. the iap supports the following commands: 1. chip-erase 2. partition0-erase 3. sector-erase 4. byte-program 5. byte-verify 6. secure page (page-level security command) secure-page 0, 1, 2, 3, 4 7. secure chip (chip-level security command) disable-extern-iap disable-extern-boot disable-extern-movc disable-extern-host-cmd 8. enable clock double 9. boot option command boot-from user-vector boot-from-zero set-user-boot-vector note: vil = input low voltage: vih = input high voltage; vih1 = input high voltage (xtal, rst); x = don?t care; al = address low order byte ; ah = address high order byte; di = data input; do = data output. table 4-1: product identification address data manufacturer?s id 30h bfh device id 31h f7h device id (extended) 32h a0h t4-1.0 1323 table 4-2: iap commands operation sfcm [6:0] sfah sfal sfdt chip-erase 01 xx xx 55 partition0-erase 0d xx xx 55 sector-erase 0b ah al xx byte-program 0e ah al di byte-verify (read) 0c ah al do secure-page0 03 90 xx xx secure-page1 03 91 xx xx secure-page2 03 92 xx xx secure-page3 03 93 xx xx secure-page4 03 94 xx xx disable-extern-iap 05 b0 xx xx disable-extern-boot 05 b1 xx xx disable-extern-movc 05 b2 xx xx disable-extern-host- cmd 05 b3 xx xx enable-clock-double 08 e0 xx xx boot-from-user-vector 08 e1 xx xx boot-from-zero 08 e2 xx xx set-user-boot-vector 09 f0 xx di t4-2.0 1294
34 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 4.2.1 iap command sequence in order to protect the flash during the power-off conditi on, the application needs to write a special, sequential command sequence to the sfcm sfr address before issuing a valid iap command. all of the following commands can only be initiated in the iap mode. in all situations, writing the control byte to the sfcm register will initiate all of the operations. a feed sequence is required prior to issuing commands through sfcm. without the feed sequence all iap commands are ignored. sector-erase, byte-program, and byte-verify commands will not be carried out on a specific memory page if the security locks are enabled on the memory page. the byte-program command is to update a byte of flash memory. if the original flash byte is not ffh, it should first be erased with an appropriate erase command. warning: do not attempt to write (program or erase) to a sector that the code is currently fetching from. this will cause unpredictable program behavior and may corrupt program data. 4.2.1.1 chip-erase chip-erase iap command erases all bytes in both memory partitions. this command is only allowed when ea# = 0 (external memory execution). chip-erase ignores the security setting status and will erase all settings on all pages and the different chip-level security restrictions, returning the device to its unlocked state. the chip-erase command will also erase the boot vector setting. upon completion of chip-erase command, the chip will boot from the default setting. see table 4-4 for the default boot vector setting figure 4-1: chip-erase table 4-3: command sequence table action access space in iap feed sequence access flash partition 0 0x0000~0x7f ff 1. write a2h to sfis0 (097h) 2. write dfh to sfis1 (0c4h) 3. then write iap command to sfcm (0b2h) access flash partition 1 0x0000~0x 07ff 1. write a2h to sfis0 (097h) 2. write fdh to sfis1 (0c4h) 3. then write iap command to sfcm (0b2h) t4-3.0 1323 table 4-4: default boot vector settings device address sst89c58rc 0f800h t4-4.1 1323 set-up mov sfdt, #55h feed sequence mov sfis0, #a2h mov sfis1, #dfh command execution mov sfcm, #01h sfcf[7] indicates operation completion iap enable orl sfcf, #40h 1323 f37.0
preliminary specification flashflex mcu sst89c58rc 35 ?2008 silicon storage technology, inc. s71323-03-000 07/08 4.2.1.2 partition0-erase the partition0-erase command erases all bytes in memory partition 0. all security bits associated with page0-3 are also reset. figure 4-2: partition0-erase 4.2.1.3 sector-erase the sector-erase command erases all of the bytes in a sector. the sector size for the flash memory blocks is 128 bytes. the selection of the sector to be erased is determined by the contents of sfah and sfal. figure 4-3: sector-erase 4.2.1.4 byte-program the byte-program command programs data into a sin- gle byte. the address is determined by the contents of sfah and sfal. the data byte is in sfdt. figure 4-4: byte-program 4.2.1.5 byte-verify the byte-verify command allows the user to verify that the device has correctly performed an erase or pro- gram command. byte-verify command returns the data byte in sfdt if the command is successful. the previous flash operation has to be fully completed before a byte-verify command can be issued. figure 4-5: byte-verify set-up mov sfdt, #55h iap enable orl sfcf, #40h command execution mov sfcm, #0dh sfcf[7] indicates operation completion 1323 f38.0 feed sequence mov sfis0, #a2h mov sfis1, #dfh program sector address mov sfah, #sector_addressh mov sfal, #sector_addressl command execution mov sfcm, #0bh sfcf[7] indicates operation completion 1323 f39.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh move data to sfdt mov sfdt, #data command execution mov sfcm, #0eh sfcf[7] indicates operation completion program byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 1323 f40.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh mov sfcm, #0ch sfdt register contains data program byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 1323 f41.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh
36 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 4.2.1.6 secure-page0, secure-page1, secure- page2, secure-page3, and secure-page4 secure-page0, secure-page1, secure-page2, secure- page3, and secure-page4 commands are used to pro- gram the page security bits. upon completion of any of these commands, th e page security options will be updated immediately. page security bits previously in un-programmed state can be programmed by these commands. the factory setting for these bits is all ?1?s which indicates the pages are not security locked. figure 4-6: secure-page0-4 4.2.1.7 enable-clock-double enable-clock-double command is used to make the mcu run at 6 clocks per machine cycle. the standard (default) is 12 clocks per machine cycle (i.e. clock dou- ble command disabled). figure 4-7: enable-clock-double select page secure_page0: mov sfah, #90h secure_page1: mov sfah, #91h secure_page2: mov sfah, #92h secure_page3: mov sfah, #93h secure_page4: mov sfah, #94h sfcf[7] indicates operation complete command execution mov sfcm, #03h 1323 f42.0 iap enable orl sfcf, #40h feed sequence mov sfis0, #a2h mov sfis1, #dfh program enable-clock-double command execution mov sfcm, #08h sfcf[7] indicates operation complete 1323 f43.0 iap enable orl sfcf, #40h set-up enable-clock-double mov sfah, #e0h feed sequence mov sfis0, #a2h mov sfis1, #dfh
preliminary specification flashflex mcu sst89c58rc 37 ?2008 silicon storage technology, inc. s71323-03-000 07/08 4.3 in-system programming the bootstrap loader (bsl) is located in partition 1 and cannot be accessed unless the sfr auxr1 (address = a2h), bit 5 is enabled. the def ault value of this bit after reset is ?1? unless the ?boot-from-zero? bit is non-zero dur- ing reset, or p1.0 and p1.1 are pulled low while ea# is held high on the falling edge of the reset. 4.3.1 normal mode if the ?boot-from-zero? bit is ?0?, the mcu boots from 0x0000. if both the ?boot-from-zero? bit and the ?boot- from-user-vector? bit are ?1?, the user boot vector is applicable (0xf800). if the ?boot-from-zero? bit is ?1? and the ?boot-from-user- vector? bit is ?0?, the user boot vector is applicable. this is used as the high byte of the program counter (pc) starting address while the lower byte of pc is 00h. see figure 4-8. figure 4-8: boot sequence flowchart 1337 f61.1 power-on external boot (ea)? default boot vector 0x0000 no hardware active both p1.0, p1.1 are low no external rom 0x0000 ?boot-from-zero? bit = 0? no ?boot-from-user- vector? = 0? no ye s ye s user boot vector ye s
38 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 4.3.2 hardware enter mode the hardware checks p1.0 and p1.1 at the falling edge of the reset. if both p1.0 and p1.1 are ?0?, then the program starts based on the boot vector value regardless of the boot vector jumper bit value. the software checks the boot status bit in the sfcf register to determine whether the latest boot was based on the hardware enter mode. see figure 4-9. figure 4-9: hardware enter mode 300 cycles ea# reset 1294 f62.0 300 cycles p1.1 p1.0
preliminary specification flashflex mcu sst89c58rc 39 ?2008 silicon storage technology, inc. s71323-03-000 07/08 5.0 timers/counters 5.1 timers the device has three 16-bit registers that can be used as either timers or event counters. the three timers/counters are denoted timer 0 (t0), timer 1 (t1), and timer 2 (t2). each is designated a pair of 8-bit registers in the sfrs. the pair consists of a most sign ificant (high) byte and least significant (low) byte. the respective registers are tl0, th0, tl1, th1, tl2, and th2. 5.2 timer set-up refer to table 3-6 for tmod, tcon, and t2con registers regarding timers t0, t1, and t2. the following tables pro- vide tmod values to be used to set up timers t0, t1, and t2. except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. there- fore, bit tr2 must be set separately to turn the timer on. table 5-1: timer/counter 0 mode function tmod internal control 1 1. the timer is turned on/off by setting/clearing bit tr0 in the software. external control 2 2. the timer is turned on/off by the 1 to 0 transition on int0# (p3.2) when tr0 = 1 (hardware control). used as timer 0 13-bit timer 00h 08h 1 16-bit timer 01h 09h 2 8-bit auto-reload 02h 0ah 3 two 8-bit timers 03h 0bh used as counter 0 13-bit timer 04h 0ch 1 16-bit timer 05h 0dh 2 8-bit auto-reload 06h 0eh 3 two 8-bit timers 07h 0fh t5-1.0 1323 table 5-2: timer/counter 1 mode function tmod internal control 1 external control 2 used as timer 0 13-bit timer 00h 80h 1 16-bit timer 10h 90h 2 8-bit auto-reload 20h a0h 3 does not run 30h b0h used as counter 0 13-bit timer 40h c0h 1 16-bit timer 50h d0h 2 8-bit auto-reload 60h e0h 3 not available - - t5-2.0 1323 1. the timer is turned on/off by setting/clearing bit tr1 in the software. 2. the timer is turned on/off by the 1 to 0 transition on int1# (p3.3) when tr1 = 1 (hardware control). table 5-3: timer/counter 2 mode t2con internal control 1 1. capture/reload occurs only on timer/counter overflow. external control 2 2. capture/reload occurs on timer/counter overflow and a 1 to 0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generating mode. used as timer 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h used as counter 16-bit auto-reload 02h 0ah 16-bit capture 03h 0bh t5-3.0 1323
40 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 5.3 programmable clock-out a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50% duty cycle clock ranging from 122 hz to 8 mhz at a 16 mhz operating frequency (61 hz to 4 mhz in 12 clock mode). to configure timer/counter 2 as a clock generator, bit c/#t2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator fre- quency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: oscillator frequency n x (65536 - rcap2h, rcap2l) n = 2 (in 6 clock mode) 4 (in 12 clock mode) where (rcap2h, rcap2l) = the contents of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode, timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate gen- erator and a clock generator simultaneously. note, how- ever, that the baud-rate and the clock-out frequency will not be the same. 6.0 serial i/o 6.1 full-duplex, enhanced uart the device serial i/o port is a full-duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respec- tively, while the software is performing other tasks. the transmit and receive registers are both located in the serial data buffer (sbuf) special function register. writ- ing to the sbuf register loads the transmit register, and reading from the sbuf register obtains the contents of the receive register. the uart has four modes of operation which are selected by the serial port mode specifier (sm0 and sm1) bits of the serial port control (scon) special function register. in all four modes, transmission is initiated by any instruction that uses the sbuf register as a destination register. reception is initiated in mode 0 when the receive interrupt (ri) flag bit of the serial port control (scon) sfr is cleared and the reception enable/ disable (ren) bit of the scon register is set. receptio n is initiated in the other modes by the incoming start bit if the ren bit of the scon register is set. 6.1.1 framing error detection framing error detection is a feature, which allows the receiving controller to check for valid stop bits in modes 1, 2, or 3. missing stops bits can be caused by noise in serial lines or from simultaneous transmission by two cpus. framing error detection is selected by going to the pcon register and changing smod0 = 1 (see figure 6-1). if a stop bit is missing, the fram ing error bit (fe) will be set. software may examine the fe bit after each reception to check for data errors. after the fe bit has been set, it can only be cleared by software. valid stop bits do not clear fe. when fe is enabled, ri rises on the stop bit, instead of the last data bit (see figure 6-2 and figure 6-3).
preliminary specification flashflex mcu sst89c58rc 41 ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 6-1: framing error block diagram figure 6-2: uart timings in mode 1 figure 6-3: uart timings in modes 2 and 3 1323 f05.0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri smod0 smod1 pof gf1 gf0 pd idl scon (98h) pcon (87h) set fe bit if stop bit is 0 (framing error) (smod0 = 1) sm0 to uart mode control (smod0 = 0) to uart framing error control bof start bit rxd ri smod0=x fe smod0=1 d0 d1 d2 d3 d4 d5 d6 d7 data byte stop bit 1323 f06.0 start bit rxd ri smod0=1 fe smod0=1 ri smod0=0 d0 d1 d2 d3 d4 d5 d6 d7 d8 data byte ninth bit stop bit 1323 f07.0
42 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 6.1.2 automatic address recognition automatic address recognition (aar) helps to reduce the time and power required to communicate with multiple serial devices. each device shares the same serial link, but has its own address. in this configuration, a device is only interrupted when it receives its own address, thus eliminat- ing the software overhead to compare addresses. this same feature helps to save power because it can be used in conjunction with idle mode to reduce the system?s overall power consumption. aa r allows the other slaves to remain in idle mode while only one is interrupted. by limit- ing the number of interruptions, the total current draw on the system is reduced. there are two ways to communicate with slaves: a group of them at once, or all of them at once. to communicate with a group of slaves, the master sends out an address called the given address. to communicate with all the slaves, the master sends out an address called the ?broadcast? address. aar can be configured as mode 2 or 3 (9-bit modes) and setting the sm2 bit in scon. each slave has its own sm2 bit set waiting for an address byte (9th bit = 1). the receive interrupt (ri) flag will only be set when the received byte matches either the given address or the broadcast address. next, the slave then clears its sm2 bit to enable reception of the data bytes (9th bit = 0) from the master. when the 9th bit = 1, the master is sending an address. when the 9th bit = 0, the mast er is sending actual data. if mode 1 is used, the stop bit takes the place of the 9th bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. note that mode 0 cannot be used. set- ting sm2 bit in the scon register in mode 0 will have no effect. each slave?s individual address is specified by sfr saddr. sfr saden is a mask byte that defines ?don?t care? bits to form the given address when combined with saddr. see the example below: 6.1.2.1 using the given address to select slaves any bits masked off by a 0 from saden become a ?don?t care? bit for the given address. any bit masked off by a 1, becomes anded with saddr. the ?don?t cares? provide flexibility in the user-defined addresses to address more slaves when using the given address. shown in the example above, slave 1 has been given an address of 1111 0001 (saddr). the saden byte has been used to mask off bits to a given address to allow more combinations of selecting slave 1 and slave 2. in this case for the given addresses, the last bit (lsb) of slave 1 is a ?don?t care? and the last bit of slave 2 is a 1. to communi- cate with slave 1 and slave 2, the master would need to send an address with the last bit equal to 1 (e.g. 1111 0001) since slave 1?s last bit is a don?t care and slave 2?s last bit has to be a 1. to communicate with slave 1 alone, the master would send an address with the last bit equal to 0 (e.g. 1111 0000), since slave 2?s last bit is a 1. see the tables below for other possible combinations. if the user added a third slave such as the example below: select slave 1 only slave 1 given address possible addresses 1111 0x0x 1111 0000 1111 0100 select slave 2 only slave 2 given address possible addresses 1111 0xx1 1111 0111 1111 0011 select slaves 1 and 2 slaves 1 and 2 possible addresses 1111 0001 1111 0101 slave 1slave 2slave 3 saddr = 1111 0001 saddr = 1111 0011 saddr = 1111 saden = 1111 1010 saden = 1111 1001 saden = 1111 given = 1111 0x0x given = 1111 0xx1 given = 1111
preliminary specification flashflex mcu sst89c58rc 43 ?2008 silicon storage technology, inc. s71323-03-000 07/08 the user could use the possible addresses above to select slave 3 only. another combination could be to select slave 2 and 3 only as shown below. more than one slave may have the same saddr address as well, and a given address could be used to modify the address so that it is unique. 6.1.2.2 using the broadcast address to select slaves using the broadcast address, the master can communicate with all the slaves at once. it is formed by performing a logi- cal or of saddr and saden with 0s in the result treated as ?don?t cares?. ?don?t cares? allow for a wider range in defining the broad- cast address, but in most cases, the broadcast address will be ffh. on reset, saddr and saden are ?0?. this produces an given address of all ?don?t cares? as well as a broadcast address of all ?don?t cares.? this effectively disables auto- matic addressing mode and allows the micro controller to function as a standard 8051, which does not make use of this feature. select slave 3 only slave 2 given address possible addresses 1111 x0x1 1111 1011 1111 1001 select slaves 2 and 3 only slaves 2 and 3 possible addresses 1111 0011 slave 1 1111 0001 = saddr +1111 1010 = saden 1111 1x11 = broadcast
44 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 6.2 enhanced smbus interface the sst89c58rc includes two enhanced subus inter- faces. the enhanced smbus uses two wires (sda and scl) to transfer information between devices connected to the bus. 6.2.1 subus features ? only two lines required (sda and scl) ? master and slave modes ? 7-bit slave address support ? supports 0-400 kbit data transfer speed ? scl line low duration time-out ? bus idle state detection interrupt ? scl configurable duty cycle ? sda line hold time configuration 6.2.2 smbus description the sst89c58rc complies with the system manage- ment bus specification, version 2.0. reads and writes are byte oriented with the smbus interface to independently control the serial transfer of data from the system controller to the interface. see figure 6-4 for a typical smbus configu- ration. by using the system clock as the bit rate clock source, data is transferred at speeds up to 400 kbits per second as a master or a slave. however, when using the timer1 as the bit rate clock source, data transfer is reduced to speeds only up to 200 kbits. these data transfer speeds are faster than those specified by the smbus specifications. a typical smbus configuration is shown in figure 6-4 and figure 6-5 shows how data transfer is accomplished on the bus. figure 6-4: typical smbus configuration figure 6-5: data transfer on the subus 1323 f44.0 p1.7/sda p1.6/scl sst89c58rc with smbus other device with smbus interface r p r p v dd smb us sda scl other device with smbus interface start condition sda stop condition 1323 f45.0 scl 9 3-8 2 1 2 19 8 7 p/s repeated start condition ack from rec ack from rec msb slave address s r/w direction bit repeated if more bytes are transferred
preliminary specification flashflex mcu sst89c58rc 45 ?2008 silicon storage technology, inc. s71323-03-000 07/08 6.2.2.1 sda (serial data line) the sda line is the smbus seri al data line, and is primarily driven by the master or slave transmitter. the sda is changeable when scl is low, and sda is stable when scl is high. perform bus arbitration on sda when scl is high. 6.2.2.2 scl (serial clock line) the scl line is the smbus serial clock line which provides synchronized transmissions between master and slave devices and is driven by the master devices. when multiple masters drive the scl simultaneously, a wired-and com- bines all signals into one sync hronized clock signal. the slowest clock determines the synchronized low period and the fastest clock determines the high period. 6.2.3 smbus modes of operation the smbus transaction begins with a start which is fol- lowed by an address byte and data, and then ends with a stop. an acknowledge bit from the receiver follows the address byte, which consists of a 7-bit address plus a direction bit, and each data byte. the direction bit (r/w), which occupies the least sign ificant bit position of the address, indicates a read operation when set to logic ?1?, and a write operation when set to logic ?0?. the master can address multiple slaves simultaneously using a general call address (0x00 + r/w), which is recognized by all slave devices. the master initiates all transactions with one or more tar- get-addressed slave devices. after generating a start condition, the master transmits the address and direction bit. for a master-to-slave write operation, data is trans- mitted a byte at a time from the master; waiting for an acknowledge after each byte from the slave. for a slave-to- master read operation, the slave awaits an acknowledge after each byte from the master. the master generates a stop which ends the transaction and frees the bus at the completion of the data transfer. at any time, the smbus is configured to operate in either master or slave mode. 6.2.3.1 master transmitter mode the serial data is output through sda while scl supplies the serial clock. the first trans mitted byte contains the slave address and the data direction bit. in this write operation mode, the data direction bit (r /w) will be logic ?0? and the master transmits serial data. after each byte is transmitted, an acknowledge bit is received from the slave. start and stop conditions are output by the master to indicate the beginning and the end of a serial transfer. 6.2.3.2 master receiver mode the serial data is received via sda while scl supplies the serial clock. the first master -transmitted byte contains the slave address and the data direction bit. in this read mode, the data direction bit (r /w) will be logic ?1?. serial data is received from the slave via sda while scl outputs the serial clock from the master. after each byte is received from the slave, an acknowledge bit is transmitted by the master. start and stop conditions are output to indicate the beginning and end of a serial transfer. 6.2.3.3 slave receiver mode the serial data is output through sda while scl supplies the serial clock. the first transmitted byte contains an address and the data direction bit. in this read mode, the data direction bit (r/w) will be logic ?1?. serial data is trans- mitted to the master if the address received matches the slave?s assigned address or if a general call address is received. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. 6.2.3.4 slave transmitter mode the serial data is received via sda while scl supplies the serial clock. the first transmitted byte contains an address and the data direction bit. in this write operation mode, the data direction bit (r/w) w ill be logic ?0?. serial data is transmitted to the master if the address received matches the slave?s assigned address or if a general call address is received. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. 6.3 timeouts 6.3.1 scl low timeout use the toe bit to enable monitoring of the scl low time- out function. when the toe is set, the smbus controls the timer1 to count during every scl low period. at every falling-edge of the scl, a reload counter pulse is gener- ated to timer1. at every rising-edge of the scl, a count stop pulse is generated to timer1. if the timer1?s counter is reloaded and counting, the last count stop pulse will cause the timer1 to generate an interrupt for scl low timeout. 1 = scl low timeout enable 0 = scl low timeout disabled
46 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 6.3.2 scl high (smbus free) timeout according to smbus specifications, the bus is designated as free if the device holds the scl and sda lines high for more than 10 smbus bit rate cycles . 6.4 smbus sfr the sst89c58rc has two identical smbus interfaces, each identical with the exception of the sfr addresses and the i/o pins associated with each interface. the smbus interfaces operate as a master and/or slave and can function on a bus with multiple masters. the smbus controls the sda, the generation and synchroniza- tion of the scl, the arbitration logic, and the control and generation of start/stop. the following sfrs are asso- ciated with the smbus. 6.4.1 smbus control register smbus control register sm0con0 configures and controls the smbus interface making all bits in the register software readable and writable. the smbus hardware sets the serial interrupt flag (si_0, smcon0.4) to logic ?1? when a valid serial interrupt condition occurs; and clears the stop flag (sto_5, sm0con0.4) to logic ?0? when a stop condi- tion is present on the bus. enable the smbus interface, by setting the smben_0 flag to logic ?1?; disable and remove it from the bus by clearing the ensmb flag to logic ?0?. to reset the smbus communi- cation, momentarily clear the smben flag and then reset it to logic ?1?. using smben to temporarily remove a device from the bus will result in lost information. the best method to temporarily remove a device from the bus is to use the assert acknowledge (aa) flag. if the bus is idle, smbus generates a start condition after a delay of 1.5 baud rate clock cycle when the start flag (sta_0, sm0con0.6) is set. if sta and stady bits are both set in the first transmission (that is, the smben is set from ?0? to ?1?) and bus is idle, a start condition will be generated after 10 baud rate clock cycles. if smbus is already in the master mode and one or more than one bytes has been transmitted or received, a repeated start condition will be generat ed when sta bit is set. if smbus is in addressed slave mode and the sta is set, no start condition will be generated until smbus enters ?not addressed slave? mode and the bus is idle. sta bit only can be cleared by software. in master mode, a stop condition is transmitted on the bus when the stop flag (sto_0, sm0con0.5) is set. and sto bit is cleared by hardware automatically after a stop condition is detected on the bus. if sta and sto bits are both set, the stop condition is transmitted firstly, and then the start condition is transmitted. in slave mode, sto is set to recover smbus from an error condition or generate a internal stop for a forced access to the bus. no stop conditi on will be transmitted on the bus and the hardware behaves as if a stop condition has been received, smbus switches to ?not addressed? slave receiver mode. sto bit is cleared by hardware after one system clocks. sto bit can not be set when smben is zero. the serial interrupt flag (si_0, sm0con0.4) can be set in any possible smbus status except for status ?0xd0? and status ?0xf8. if ea and es1 bits are set, an interrupt will requested when si is set. when si flag is set by hardware, the scl line is held to low until it is cleared by software (except for the status ?0xd0? , which will not hold the scl line low). only ?0? can be written to clear si flag, writing ?1? has no effect to the flag. when si flag is cleared, smbsta register changes to ?0xf8?. during the acknowledge clock cycle on the scl line, the assert acknowledge flag (aa_0, sm0con0.3) sets the level of the sda line. in slave transmitter mode, the aa flag is used to determine whether the last data byte will be transmitted or enables whether to respond its slave address or general call address. in master receiver mode, the aa flag is used to determine to return ack or nack after receiving a byte. in slave receiver mode, the aa flag is used to determine to return ack or nack and enables whether to respond its slave address or general call address. table 6-1: smbus sfr functions sfr function sm0con0 / sm0con1 configures smbus0 sm0sta controls status of smbus0 sm0dat data register for transmitting and receiving smbus0 data sm0adr indicates smbus0 slave address sm0sclh / sm0scll configures smbus0 high/low duty sm1con0 / sm1con1 configures smbus1 sm1sta controls status of smbus1 sm1dat data register for transmitting and receiving smbus1 data sm1adr indicates smbus1 slave address sm1sclh / sm1scll configures smbus1 high/low duty t6-1.1323
preliminary specification flashflex mcu sst89c58rc 47 ?2008 silicon storage technology, inc. s71323-03-000 07/08 1 = when set to 1, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line on the following situations: 3. the ?own slave address? has been received. 4. the general call address has been received while the general call bit (gc) in smbadr is set. 5. a data byte has been received while the smbus interface is in the master receiver mode. 6. a data byte has been received while the smbus interface is in the addressed slave receiver mode. 0 = when cleared to 0, an non-acknowledge (high level to sda) will be returned during the acknowledge clock pulse on the scl line on the following situations: 1. a data byte has been received while the smbus interface is in the master receiver mode. 2. a data byte has been received while the smbus interface is in the addressed slave receiver mode. to enable the smbus free timeout feature, set the smbus free timer enable bit (fte, sm0con0.2) to logic ?1?. the bus is considered free and, if pending, a start is generated when scl and sda remain high for the smbus free time- out given in the smbus clock rate register. to enable monitoring scl low timeout function, set the smbus time out enable bit (toe_0, sm0con0.1) to logic ?1?. when toe is set, smbus will control the timer1 to count during the every scl low period. at every scl fall- ing-edge of the scl, a reload counter pulse is generated to timer1; at every scl rising-edge of the scl, a count stop pulse is generated to timer1. if the timer1?s counter is reloaded and counting, the latest count stop pulse will cause the timer1 to generate an interrupt for scl low timeout. 6.4.2 data register the smbus data register (sm0dat0) holds a byte of recently received or ready-to-transmit serial data. when si is set to logic ?1?, the data in the register is stable. in this state, software safely reads or writes the data register. however, when the smbus is enabled and the si flag is cleared to logic ?0?, the software must not access the sm0dat register because the hardware may be shifting a data byte in or out of the register. after the sm0dat receives a byte of data, the first bit of the serial data byte is located at the msb. as data is shifted out of the sm0dat, beginning with the msb, data from the bus is simultaneously shifted in. the last data byte on the bus is always contained in the sm0dat; thereby, ensuring that correct data is transmitted from the master to the slave in the event of lost arbitration. 6.4.3 address register the slave address is held in the sm0adr address regis- ter. when in slave mode, the 7-bit address is held in the seven most significant bits, the least of which is bit 0. bit 0 recognizes the general call address (0x00) when set to logic ?1?. when the smbus hardware is operating in master mode, the contents of the sm0adr address register are ignored. 6.4.4 status register the status of the smbus is held in the sm0sta status reg- ister as one of 31 different 8-bit status codes. each 8-bit status code corresponds to a unique smbus state. when si = ?1?, the three least significant bits of the status code are set to zero and the five most significant bits vary. all possi- ble status codes are multiples of eight; which, in software, allows the status code to act as an index to branch to ser- vice routines by allowing 8 bytes of code to service the state or jump to a more extensive routine. set the si flag to logic ?1? to define the contents of the sm0sta register for software use. software must not write to the sm0sta because doing so yields uncertain results. refer to tables 6-1 through 6-4 for the 31 smbus states and their corresponding status codes.
48 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 6-2: master transmitter mode status code (sm0sta) smbus1 hardware status application software response smbus hardware - next action to/from sm0dat to sm0con sta sto si aa 08h start condition transmitted load sla+w x 0 0 x sla+w transmitted; ack bit received 10h repeat start transmitted load sla+w or x 0 0 x sla+w transmitted; ack bit received load sla+r x 0 0 x sla+w transmitted; smbus switched to mst/rec mode 18h sla+w transmitted; ack received load data byte or 0 0 0 x data byte transmitted; ack received no sm0dat action 1 0 0 x repeat start transmitted 0 1 0 x stop condition transmitted sto flag reset 1 1 0 x stop condition followed by start condition transmitted; sto flag reset 20h sla+w transmitted; not ack received load data byte or 0 0 0 x data byte transmitted; ack bit received no sm0dat action 1 0 0 x repeat start transmitted 0 1 0 x stop condition transmitted; sto flag reset 1 1 0 x stop condition followed by start condition transmitted; sto flag reset 28h data byte in sm0dat trans- mitted; ack received load data byte or 0 0 0 x data byte transmitted; ack bit received no sm0dat action 1 0 0 x repeat start transmitted 0 1 0 x stop condition transmitted; sto flag reset 1 1 0 x stop condition followed by start condition transmitted; sto flag reset 30h data byte in sm0dat trans- mitted; not ack received load data byte or 0 0 0 x data byte transmitted; ack bit received no sm0dat action 1 0 0 x repeat start transmitted 0 1 0 x stop condition transmitted; sto flag reset 1 1 0 x stop condition followed by start condition transmitted; sto flag reset 38h arbitration lost in sla+rw or data bytes no sm0dat action 0 0 0 x smbus released; non-addressed slave entered 1 0 0 x a start condition is transmitted once the bus is free t6-2.1323
preliminary specification flashflex mcu sst89c58rc 49 ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 6-3: master receiver mode status code (sm0sta) smbus hardware status application software response smbus hardware - next action to/from sm0dat to sm0con sta sto si aa 08h start condition transmitted load sla+w x 0 0 x sla+w transmitted; ack bit received 10h repeat start transmitted load sla+w or x 0 0 x sla+w transmitted; ack bit received load sla+r x 0 0 x sla+w transmitted; smbus switched to mst/trx mode 38h arbitration lost in not ack bit no sm0dat action 0 0 0 x smbus released; smbus enters slave mode 1 0 0 x a start condition is transmitted once the bus is free 40h sla+r transmitted; ack received no sm0dat action 0 0 0 0 data byte received; not ack bit returned 0 0 0 1 data byte received; ack bit returned 48h sla+r transmitted; not ack received no sm0dat action 1 0 0 x repeat start transmitted 0 1 0 x stop condition transmitted; sto flag reset 1 1 0 x stop condition followed by start condition transmitted; sto flag reset 50h data byte received; ack returned read data byte 0 0 0 0 data byte received; not ack bit returned 0 0 0 1 data byte received; ack bit returned 58h data byte received; not ack returned read data byte 1 0 0 x repeat start transmitted 0 1 0 x stop condition transmitted; sto flag reset 1 0 0 x stop condition followed by start condition transmitted; sto flag reset t6-3.1323
50 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 6-4: slave receiver mode status code (sm0sta) smbus hardware status application software response smbus hardware - next action to/from sm0dat to sm0con sta sto si aa 60h own sla+w received; ack returned no sm0dat action x 0 0 x data byte received; not ack bit returned x 0 0 1 data byte received; ack returned 68h arbitration lost in master sla+r/w; own sla+w received, ack returned no sm0dat action x 0 0 0 data byte received; not ack bit returned x 0 0 1 data byte received; ack returned 70h general call address (00h) received; ack returned no sm0dat action x 0 0 0 data byte received; not ack bit returned x 0 0 1 data byte received; ack returned 78h arbitration lost in master sla+r/w; general call address (00h) received; ack returned no sm0dat action x 0 0 0 data byte received; not ack bit returned x 0 0 1 data byte received; ack returned 80h previously slv addressed: data received; ack returned read data byte x 0 0 0 data byte received; not ack bit returned x 0 0 1 data byte received; ack returned 88h previously slv addressed: data received; not ack returned read data byte 0 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized 0 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1? 1 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized a start is transmitted once bus is free 1 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1?. a start is transmitted once bus is free 90h previously general call addressed; data byte received; ack returned read data byte x 0 0 0 data byte received; not ack bit returned x 0 0 1 data byte received; ack returned
preliminary specification flashflex mcu sst89c58rc 51 ?2008 silicon storage technology, inc. s71323-03-000 07/08 98h previously general call addressed; data byte received; ack returned read data byte 0 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized 0 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1? 1 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized a start is transmitted once bus is free 1 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1?. a start is transmitted once bus is free a0h a stop condition or a start condition received while addressed as slv/rec or slv/trx no stdat action 0 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized 0 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1? 1 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized a start is transmitted once bus is free 1 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1?. a start is transmitted once bus is free t6-4.1323 table 6-4: slave receiver mode status code (sm0sta) smbus hardware status application software response smbus hardware - next action to/from sm0dat to sm0con sta sto si aa
52 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 6-5: slave transmitter mode status code (sm0sta) smbus hardware status application software response smbus hardware - next action to/from sm0dat to sm0con sta sto si aa a8h own sla+r received; ack returned load data byte x 0 0 0 last data byte transmitted; ack received x 0 0 1 data byte transmitted; ack received b0h arbitration lost in master sla+r/w; own sla+r received, ack returned load data byte x 0 0 0 last data byte transmitted; ack received x 0 0 1 data byte transmitted; ack received b8h sm0dat data byte transmit- ted; ack received load data byte x 0 0 0 last data byte transmitted; ack received x 0 0 1 data byte transmitted; ack received c0h sm0dat data byte transmit- ted; not ack received no sm0dat action 0 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized 0 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1? 1 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized a start is transmitted once bus is free 1 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1?. a start is transmitted once bus is free c8h sla+r transmitted; not ack received no sm0dat action 0 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized 0 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1? 1 0 0 0 switch to non-addressed slv mode; own sla / general call address not recognized a start is transmitted once bus is free 1 0 0 1 switch to non-addressed slv mode; recognizes own sla; recognizes gen- eral call address if sm0adr.0 = logic ?1?. a start is transmitted once bus is free t6-5.1323
preliminary specification flashflex mcu sst89c58rc 53 ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 6-6: miscellaneous status status code (sm0sta) smbus hardware status application software response smbus hardware - next action to/from sm0dat to sm0con sta sto si aa f8h no available state informa- tion; si = ?0? no sm0dat action no sm0con action wait or proceed with current transfer 00h bus error during mst or selected slave modes caused by illegal start or stop; or smbus entered an undefined state no sm0dat action 0 1 0 x only internal hardware is affected in the smt or addressed slv modes. in all cases, the bus is released and smbus is switched to the not addressed slv mode. sto is reset. d0h scl high timeout no sm0dat action x x 0 x si flag is cleared. the next work con- tinues. t6-6.1323
54 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 6-6: smbus serial interface block diagram 8 ack shift register comparator timi n g & co n trol logic i n terrupt status register status decoder co n trol register serial clock ge n erator timer 1 o v erflo w status bus arbitratio n & sy n c logic i n put filter output filter i n put filter output filter p1.5/p1.6 p1.7/p1.4 8 8 i n ter n al bus 8 sm0co n sm0scll sm0sclh sm0sta cclk sm0adr sm0dat sda scl 1323 f46.1 address register
preliminary specification flashflex mcu sst89c58rc 55 ?2008 silicon storage technology, inc. s71323-03-000 07/08 6.4.5 smbus scl high and low duty sm0sclh sets the scl high duration and sm0scll sets the scl low duration. the sm0sclh and sm0scll reg- isters must be set to select the bit rate when the internal clock source for the smbus scl is selected. to select the internal serial clock source for the sm0cll, set crsel = ?0? in the sm0con0 register. bit rate = f pclk / (4 x (sm0sclh + sm0scll)) the registers can be set to different duty cycles for the scl. while the values for the sm0sclh and sm0scll registers can be different, the value of the registers must keep the data rate in a data rate range of 0-400 khz, and ensure that the scl high period is no less than 600ns and the low period is no less than 1000ns. the values for both sm0sclh and sm0scll should be at least three. timer1 is used as the bit rate clock source when srsel is set. to generate the periodic pulse signal that the smbus uses to generate the bit rate clock, configure timer1 to mode 2. when timer1 is used, the bit rate is calculated as: bit rate = f pclk / (96 x (256 - th1)) th1 and tl1 are the high and low bytes counters for timer1. in mode 2, when tl1 counts to 0xff, the value of th1 is automatically reloaded into tl1. table 6-7: bit rate configuration 1 1. scl bus rise transition time (t r ) must be less than 300 ns. sm0sclh 2 / sm0scll 3 2. sm0sclh minimum value is 1400 ns/(4*cycsysclk), but cannot be less than 3. 3. sm0scll minimum value is 1100 ns/(4*cycsysclk), but cannot be less than 3. crsel bit rate 4 (kbit/s) at f pclk 4. baud rate setting must not exceed 400 kbit per second. 6mhz 12mhz 33mhz 40mhz 6250--- 8 0 188 375 - - 15 0 100 200 - - 25 0 60 120 330 400 40 0 38 75 197 250 50 0 30 60 165 200 100 0 15 30 83 100 150 0 102055 67 200 0 8 15 42 50 250 0 6 12 33 40 300 0 5 10 28 34 400 0 4 8 21 25 510 0 3 6 16 20 bit rate (timer1 5 in mode2) 5. if using timer1 as the baud rate clock source, th1 must be 0- 254 if the system clock is higher than 20 mhz. if the system clo ck is lower than or equal to 20 mhz, th1 can only be 0-255. 0.25-63kbps 0.49-125kbps 1. 34-172kbps 1.63-208kbps t6-7.1323
56 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 7.0 watchdog timer the programmable watchdog timer (wdt) is for fail safe protection against software deadlock and for automatic recovery. the watchdog timer is utilized as a watchdog or a timer. to use the watchdog timer as a watchdog, set wdre (wdtc[3]) to ?1?. to use the watchdog timer as a timer only, set wdre to ?0? so timer overflows generate an inter- rupt. set ewd (iea[6]) to ?1? to enable the interrupt. 7.1 watchdog timer mode to protect the system against software deadlock, wdt (wdtc[1]) should be refreshed within a user-defined time period. without a periodic refresh, an internal hardware reset will initiate when wdre (wdtc[3]) = 1). only a power-on reset clears the wdre bit. any write to wdtc must be preceded by a correct feed sequence. if wdton (wdtc[6])=0, the start or stop of the watchdog is controlled by swdt (wdtc[0]). if wdton = 1, the watchdog starts regardless of swdt and cannot be stopped until overflowed. the upper 8 bits of the time base register (wdtd) is used as the reload register of the counter. when wdt (wdtc[1]) is set to ?1?, the content of wdtd is loaded into the watchdog counter and the prescaler is cleared. if a watchdog reset occurs, the reset pin will output at least 196 system clocks. the code execution will begin immedi- ately after the reset cycle. the wdts flag bit is set by the watchdog timer overflow and can only be cleared by power-on reset. users can also clear the wdts bit by writing ?1? to it following a correct feed sequence. 7.2 pure timer mode in timer mode, the wdtc and wdtd can be written at any time without a feed sequence. setting or clearing the swdt bit will start or stop the counter. a timer overflow will set the wdts bit. writing ?1? to this bit clears it. when an overflow occurs, the content of wdtd is reloaded into the counter and the watchdog ti mer immediately begins to count again. if the interrupt is enabled, an interrupt will occur when the timer overflows. the vector address is 053h and it has a nine-level priority by default. a feed sequence is not required in this mode. 7.3 clock source the wdt in the device uses the system clock (xtal1) as its time base, making it a watchdog counter rather than a watchdog timer. the wdt regi ster will increment every 344,064 crystal clocks. the upper 8-bits of the time base register (wdtd) are used as the reload register of the wdt. figure 7-1 provides a block diagram of the wdt. two sfrs (wdtc and wdtd) control watchdog timer operation. the time-out period of the wdt is calculated as follows: period = (255 - wdtd) * 344064 * 1/f clk (xtal1) where wdtd is the value loaded into the wdtd register and f osc is the oscillator frequency. 7.4 feed sequence in watchdog mode (wdre=1), a feed sequence is needed to write into the wdtc register. the correct feed sequence is: 1. write fdh to sfis1, 2. write 2ah to sfis0, then 3. write to the wdtc register an incorrect second or third instruction of the feed sequence causes an immediat e reset in watchdog mode. in timer mode, the wdtc and wdtd can be written at any time. a feed sequence is not required. 7.5 power saving considerations for using the watchdog timer during idle mode, the watchdo g timer will remain active. the device should be awakened and the watchdog timer refreshed periodically before expiration. during power- down mode, the watchdog timer is stopped. when the watchdog timer is used as a pur e timer, users can turn off the clock to save power. see ?power management control register (pmc)? on page 25.
preliminary specification flashflex mcu sst89c58rc 57 ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 7-1: block diagram of programmable watchdog timer 1323 f47.0 wdt upper byte wdt reset internal reset 344064 clks counter clk (xtal1) ext. rst wdtc wdtd
58 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 8.0 security lock the security lock protects against software piracy and pre- vents the contents of the flash from being read by unautho- rized parties. it also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. there are two different types of security locks in the device security lock system: chip- level security lock and page-level security lock. 8.1 chip-level security lock there are four types of chip-level security locks. 1. disable external movc instruction 2. disable external host mode (except read chip id and chip-erase commands) 3. disable boot from external memory 4. disable external iap commands (except chip- erase commands) users can turn on these security locks in any combination to achieve the security protection scheme. to unlock secu- rity locks, the chip-erase command must be used. 8.1.1 disable external movc instruction when disable-extern-movc command is executed either by external host mode command or iap mode command, movc instructions executed from external program mem- ory are disabled from fetching code bytes from internal memory. 8.1.2 disable external host mode when disable-extern-host-cmd command is executed either by external host mode command or iap mode command, all external host mode commands are disabled except chip-erase command and read-id command. upon activation of this op tion, the device can not be accessed through external host mode. user can not verify and copy the contents of the internal flash 8.1.3 disable boot from external memory when disable-extern-boot command is executed either by external host mode command or iap mode command, the ea pin value will be ignor ed during chip reset and always boot from the internal memory. 8.1.4 disable external iap commands when disable-extern-iap command is executed either by external host mode command or iap mode command, all iap commands executed from external memory are dis- abled except chip-erase command. all iap commands executed from internal memory are allowed if the page lock is not set. 8.2 page-level security lock when any of secure-page0, secure-page1, secure- page2, secure-page3, or secure-page4 command is exe- cuted, the individual page (page0, page1, page2, page3, or page4) will enter secured mode. no part of the page can be verified by either external host mode commands or iap commands. movc instructions are also unable to read any data from the page. to unlock the security locks on page0-3 of the primary par- tition (partition0), the partition0-erase command must be used. to unlock the security lock on page4, the chip-erase command must be used. 8.3 read operation u nder lock condition the following three cases can be used to indicate the read operation is targeting a locked, secured memory area: 1. external host mode: read-back = 55h (locked) 2. iap command: read-back = previous sfdt data 3. movc: read-back = 00h (blank)
preliminary specification flashflex mcu sst89c58rc 59 ?2008 silicon storage technology, inc. s71323-03-000 07/08 9.0 reset a system reset initializes the mcu and begins program execution at program memory location 0000h or the boot vector address. the reset input for the device is the rst pin. in order to reset the device, a logic level high must be applied to the rst pin for at least two machine cycles (24 clocks), after the oscillato r becomes stable. ale and psen# are weakly pulled high during reset. during reset, ale and psen# output a high level in order to perform a proper reset. this level must not be affected by external element. a system reset will not affect the 512 bytes of on- chip ram while the device is running, however, the con- tents of the on-chip ram during power up are indetermi- nate. following reset, all s pecial function registers (sfr) return to their reset values outlined in tables 3-3 to 3-7. 9.1 power-on reset at initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algo- rithm has weakly pulled all pins high. when power is applied to the device, the rst pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. an exam- ple of a method to extend the rst signal is to implement a rc circuit by connecting the rst pin to v dd through a 10 f capacitor and to v ss through an 8.2k resistor as shown in figure 9-1. note that if an rc circuit is being used, provisions should be made to ensure the v dd rise time does not exceed 1 millis econd and the oscillator start- up time does not exceed 10 milliseconds. for a low frequency oscillator wi th slow start-up time the reset signal must be extended in order to account for the slow start-up time. this method maintains the necessary relationship between v dd and rst to avoid programming at an indeterminate location. the pof flag in the pcon register is set to indicate an initial power up condition. the pof flag will remain active until cleared by software. please refer to section 3.5, pcon register definition, for detailed information. for more information on system level design techniques, please review the design considerations for the sst flashflex family microcontroller application note. figure 9-1: power-on reset circuit 9.2 interrupt priority and polling sequence the device supports seven interrupt sources under a four level priority scheme. table 9-1 and figure 9-2 summarize the polling sequence of the supported interrupts. 1323 f48.0 v dd v dd 10f + - 8.2k sst89c58rc rst xtal2 xtal1 c 1 c 2
60 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 9-2: interrupt sequence ie1 int1# individual enables tf1 tf0 ri 0 1 ie0 global disable highest priority interrupt interrupt polling sequence lowest priority interrup it0 it1 int0# ie & iea registers ip/iph/ipa/ipah registers 0 1 tf2 exf2 ti watchdog timer 1323 f49.0
preliminary specification flashflex mcu sst89c58rc 61 ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 9-1: interrupt table description interrupt flag vector address service priority wake-up power-down ext. int0 ie0 0003h 1(highest) yes smbus0 - 002bh 2 yes t0 tf0 000bh 3 no ext. int1 ie1 0013h 4 yes t1 tf1 001bh 5 no uart ti/ri 0023h 6 no t2 tf2, exf2 003bh 7 no smbus1 - 0043h 8 yes watchdog - 0053h 9 no t9-1.0 1323
62 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 10.0 power-saving modes the device provides two power saving modes of operation for applications where power consumption is critical. the two modes are idle and power-down, see table 10-1. 10.1 idle mode idle mode is entered setting the idl bit in the pcon regis- ter. in idle mode, the program counter (pc) is stopped. the system clock continues to run and all interrupts and periph- erals remain active. the on-chip ram and the special func- tion registers hold their data during this mode. the device exits idle mode through either a system inter- rupt or a hardware reset. exiting idle mode via system interrupt, the start of the interrupt clears the idl bit and exits idle mode. after exit the interrupt service routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. a hardware reset starts the device similar to a power-on reset. 10.2 power-down mode the power-down mode is entered by setting the pd bit in the pcon register. in the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. sram contents are retained during power- down, the minimum v dd level is 2.0v. the device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. the start of the interrupt clears the pd bit and exits power-down. holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. upon interrupt signal restored to logic v ih, the interrupt service routine program execution resumes beginning at the instruction immediately follo wing the instruction which invoked power-down mode. a hardware reset starts the device similar to power-on reset. to exit properly out of power-down, the reset or external interrupt should not be executed before the v dd line is restored to its normal operating voltage. be sure to hold v dd voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 20 ms). when the mcu is in power-down mode, a falling edge on the sda pin of the smbus will wakeup the mcu. because the first byte may not be received by the smbus correctly, the first start condition may be missed because the oscillators will not start up. table 10-1: power saving modes mode initiated by state of mcu exited by idle software (set idl bit in pcon) mov pcon, #01h; ? clk is running. ? interrupts, serial port and timers/counters are active. ? program counter is stopped. ? ale and psen# signals at a high level during idle. ? all registers remain unchanged. enabled interrupt or hardware reset. start of interrupt clears idl bit and exits idle mode, after the isr reti instruction, pro- gram resumes execution beginning at the instruction following the one that invoked idle mode. a user could consider placing two or three nop instructions after the instruction that invokes idle mode to eliminate any prob- lems. a hardware reset restarts the device similar to a power-on reset. power-down software (set pd bit in pcon) mov pcon, #02h; ? clk is stopped. ? on-chip sram and sfr data is maintained. ? ale and psen# signals at a low level during power -down. ? external interrupts are only active for level sensitive interrupts, if enabled. enabled external level sensitive interrupt or hardware reset. start of interrupt clears pd bit and exits power-down mode, after the isr reti instruction program resumes exe- cution beginning at the instruction following the one that invoked power-down mode. a user could consider placing two or three nop instructions after the instruction that invokes power-down mode to eliminate any problems. a hardware reset restarts the device similar to a power-on reset. t10-1.0 1323
preliminary specification flashflex mcu sst89c58rc 63 ?2008 silicon storage technology, inc. s71323-03-000 07/08 11.0 system clock and clock options 11.1 clock input options and recom- mended capacitor valu es for oscillator shown in figure 11-1 are the input and output of an inter- nal inverting amplifier (xtal1, xtal2), which can be con- figured for use as an on-chip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. at start-up, the external oscillator may encounter a higher capacitive load at xtal1 due to interaction between the amplifier and its feedback capacitance. however, the capacitance will not exceed 15 pf once the external signal meets the v il and v ih specifications. crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one applica- tion to another. c1 and c2 should be adjusted appropri- ately for each design. table 11-1, shows the typical values for c1 and c2 vs. crystal type for various frequencies more specific information abo ut on-chip oscillator design can be found in the flashflex oscillator circuit design considerations application note. 11.2 clock doubling option by default, the device runs at 12 clocks per machine cycle (x1 mode). the device has a clock doubling option to speed up to 6 clocks per machine cycle. please refer to table 11-2 for detail. clock double mode can be enabled either via the external host mode or the iap mode. please refer to table 4-2 for the iap mode enabling command (when cleared, the enable-clock-double bit in the sfst register will indicate 6-clock mode.). the clock double mode is only for doubling the internal sys- tem clock and the internal flash memory, i.e. ea#=1. to access the external memory and the peripheral devices, careful consideration must be taken. also note that the crystal output (xtal2) will not be doubled. figure 11-1: oscillator characteristics table 11-1: recommended values for c1 and c2 by crystal type crystal c1 = c2 quartz 20-30pf ceramic 40-50pf t11-1.1 1323 table 11-2: clock doubling features device standard mode (x1) clock double mode (x2) clocks per machine cycle max. external clock frequency (mhz) clocks per machine cycle max. external clock frequency (mhz) sst89e5xc 12 40 6 20 t11-2.0 1323 1323 f50.0 xtal2 xtal1 v ss c 1 using the on-chip oscillator external clock drive c 2 xtal2 xtal1 v ss external oscillator signal nc
64 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 12.0 electrical specification note: this specification contains preliminary information on new products in production. the specifications are subj ect to change without notice. absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c voltage on ea# pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0 v d.c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20ns) on any other pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd +1.0v maximum i ol per i/o pins p1.4, p1.5, p1.6, p1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ma maximum i ol per i/o for all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ma package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5w through hole lead soldering temperature (10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. outputs shorted for no more than one second. no more than one output shorted at a time. (based on package heat transfer limitati ons, not device power consumption. table 12-1: operating range symbol description min. max unit t a ambient temperature under bias standard 0 +70 c industrial -40 +85 c v dd supply voltage sst89c58rc 2.7 5.5 v f osc oscillator frequency sst89c58rc 0 40 mhz oscillator frequency for in-application programming sst89c58rc 25 40 mhz t12-1.1 1323 table 12-2: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t12-2.0 1323
preliminary specification flashflex mcu sst89c58rc 65 ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 12-3: ac conditions of test input rise/fall time . . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf see figures 12-5 and 12-7 t12-3.0 1323 table 12-4: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t12-4.2 1323 table 12-5: pin impedance (vdd=3.3v, ta=25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 15 pf c in 1 input capacitance v in = 0v 12 pf l pin 2 2. refer to pci spec. pin inductance 20 nh t12-5.4 1323
66 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 12.1 dc electrical characteristics table 12-6: dc characteristics for sst89c58rc: t a = -40c to +85c; v dd = 2.7-5.5v; v ss = 0v symbol parameter test conditions min max units v dd operating voltage 2.7 5.5 v v il1 input low voltage p0, p1, p2, p3, ea# 3.6v preliminary specification flashflex mcu sst89c58rc 67 ?2008 silicon storage technology, inc. s71323-03-000 07/08 12.2 ac electrical characteristics ac characteristics: (over operating cond itions: load capacitance for po rt 0, ale, and psen# = 100pf; load capacitance for all other outputs = 80pf) table 12-7: ac electrical characteristics t a = -40c to +85c, 2.7-5.5v@40mhz, v ss = 0v symbol parameter oscillator units 40 mhz (x1 mode) 20 mhz (x2 mode) 1 1. calculated values are for x1 mode only variable min max min max 1/t clcl x1 mode oscillator frequency 040 0 40 mhz 1/2t clcl x2 mode oscillator frequency 020 0 20 mhz t lhll ale pulse width 35 2t clcl - 15 ns t avll address valid to ale low 10 t clcl - 15 (5v) ns t llax address hold after ale low 10 t clcl - 15 (5v) ns t lliv ale low to valid instr in 55 4t clcl - 45 (5v) ns t llpl ale low to psen# low 10 t clcl - 15 (5v) ns t plph psen# pulse width 60 3t clcl - 15 (5v) ns t pliv psen# low to valid instr in 25 3t clcl - 50 (5v) ns t pxix input instr hold after psen# 0ns t pxiz input instr float after psen# 10 t clcl - 15 (5v) ns t pxav psen# to address valid 17 t clcl - 8 ns t aviv address to valid instr in 65 5t clcl - 60 (5v) ns t plaz psen# low to address float 10 10 ns t rlrh rd# pulse width 120 6t clcl - 30 (5v) ns t wlwh write pulse width (we#) 120 6t clcl - 30 (5v) ns t rldv rd# low to valid data in 75 5t clcl - 50 (5v) ns t rhdx data hold after rd# 00 ns t rhdz data float after rd# 38 2t clcl - 12 (5v) ns t lldv ale low to valid data in 150 8t clcl - 50 (5v) ns t avdv address to valid data in 150 9t clcl - 75 (5v) ns t llwl ale low to rd# or wr# low 60 90 3t clcl - 15 (5v) 3t clcl + 15 (5v) ns t avwl address to rd# or wr# low 70 4t clcl - 30 (5v) ns t qvwx data valid to wr# high to low transition 5t clcl - 20 ns t whqx data hold after wr# 5t clcl - 20 (5v) ns t qvwh data valid to wr# high 125 7t clcl - 50 (5v) ns t rlaz rd# low to address float 00ns t whlh rd# to wr# high to ale high 10 40 t clcl - 15 (5v) t clcl + 15 (5v) ns t ofsb smbus output fall time from vih min to vil max with a bus capacitance100pf 30 (5v) 250 (5v) ns t12-7.0 1323
68 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 explanation of symbols each timing symbol has 5 characters. the fi rst character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all t he characters and what they stand for. for example: t avll = time from address valid to ale low t llpl = time from ale low to psen# low a: address q: output data c: clock r: rd# signal d: input data t: time h: logic level high v: valid i: instruction (program memory contents) w: wr# signal l: logic level low or ale x: no longer a valid logic level p: psen# z: high impedance (float)
preliminary specification flashflex mcu sst89c58rc 69 ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 12-1: external program memory read cycle figure 12-2: external data memory read cycle 1323 f51.0 port 2 port 0 psen# ale a0 - a7 t llax t plaz t pxiz t llpl t aviv t avll t pxix t lhll t lliv t pliv t plph instr in a8 - a15 a8 - a15 a0 - a7 t pxav 1323 f52.0 port 2 port 0 rd# psen# ale t lhll p2[7:0] or a8-a15 from dph a0-a7 from ri or dpl t avdv t avwl data in instr in t rlaz t avll t llax t llwl t lldv t rlrh t rldv t rhdz t whlh t rhdx a8-a15 from pch a0-a7 from pcl
70 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 12-3: external data memory write cycle figure 12-4: shift register mode timing waveforms table 12-8: serial port timing symbol parameter oscillator units 12mhz 40mhz variable min max min max min max t xlxl serial port clock cycle time 1.0 0.3 12t clcl s t qvxh output data setup to clock rising edge 700 117 10t clcl - 133 ns t xhqx output data hold after clock rising edge 50 2t clcl - 117 ns 02t clcl - 50 ns t xhdx input data hold after clock rising edge 0 0 0 ns t xhdv clock rising edge to input data valid 700 117 10t clcl - 133 ns t12-8.2 1323 1323 f53.0 port 2 port 0 wr# psen# ale t lhll p2[7:0] or a8-a15 from dph a0-a7 from ri or dpl data out instr in t avll t avwl t llwl t llax t wlwh t qvwh t qvwx t whqx t whlh a8-a15 from pch a0-a7 from pcl 1323 f54.0 ale 0 instruction clock output data write to sbuf valid valid valid valid valid valid valid valid input data clear ri 01 2 34 567 t xlxl t qvxh t xhqx t xhdx set ti set ri 1 2 3 4 5 6 7 8 t xhdv
preliminary specification flashflex mcu sst89c58rc 71 ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 12-5: ac testing input/output test waveform figure 12-6: float waveform figure 12-7: a test load example figure 12-8: i dd test condition, active mode v lt ac inputs during testing are driven at v iht (v dd -0.5v) for logic "1" and v ilt (0.45v) for a logic "0". measurement reference points for inputs and outputs are at v ht (0.2v dd + 0.9) and v lt (0.2v dd - 0.1) v ht v iht v ilt 1323 f55.0 note: v ht - v high te s t v lt - v low test v iht -v input high test v ilt - v input low test for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh = 20ma. v load +0.1v v load -0.1v v oh -0.1v timing reference points v ol +0.1v v load 1323 f56.0 1323 f57.0 to tester to dut c l v dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected xtal1 1323 f58.0 v ss i dd sca0 scl0 sda1 scl1
72 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 12-9: i dd test condition, idle mode figure 12-10: i dd test condition, power-down mode v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected xtal1 1323 f59.0 v ss i dd sca0 scl0 sda1 scl1 table 12-9: flash memory programming/verification parameters 1 1. for iap operations, the program execution overhead must be added to the above timing parameters. the test condition shows as follows: ta = -40c to +85c, 2.7-5.5v@1mhz, vss = 0v. parameter 2 2. program and erase times will scale inversel y proportional to programming clock frequency. max units chip-erase time 50 ms block-erase time 50 ms sector-erase time 10 ms byte-program time 3 3. each byte must be erased before programming. 80 s re-map or security bit program time 100 s t12-9.0 1323 v dd v dd v dd v dd p0 ea# rst p1.4 p1.5 p1.6 p1.7 xtal2 (nc) all other pins disconnected xtal1 1323 f60.0 v ss i dd v dd = 5v
preliminary specification flashflex mcu sst89c58rc 73 ?2008 silicon storage technology, inc. s71323-03-000 07/08 13.0 product ordering information 13.1 valid co mbinations note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. device speed suffix1 suffix2 sst89 x 5xc -xx -x -xx x x environmental attribute e 1 = non-pb f 2 = non-pb, non-sn package modifier i = 40 pins j = 44 pins package type n = plcc tq = tqfp q = wqfn operation temperature i = industrial = -40c to +85c operating frequency 40 = 0-40mhz feature set rc = single block dual partitions flash memory size 8 = 34 kbyte voltage rang e c = 2.7-5.5v product series 89 = c51 core 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. 2. environmental suffix ?f? denotes non-pb/non-sn solder. sst non-pb/non-sn solder devices are ?rohs compliant?. valid combinations for sst89c58rc sst89c58rc-40-i-nje sst89c58rc-40 -i-tqje SST89C58RC-40-I-QIF
74 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 14.0 packaging diagrams figure 14-1: 44-lead plastic lead chip carrier (plcc) sst package code: nj .025 .045 .013 .021 .590 .630 .100 .112 .020 min. top view side view bottom view 144 .026 .032 .500 ref. .165 .180 44-plcc-nj-7 note: 1. complies with jedec publication 95 ms-018 ac dimensions (except as noted), although some dimensions may be more strin gent. ? = jedec min is .650; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc. .050 bsc. .026 .032 .042 .056 .646 ? .656 .042 .048 .042 .048 optional pin #1 identifier .646 ? .656 .685 .695 .685 .695 .020 r. max. .147 .158 r. x45
preliminary specification flashflex mcu sst89c58rc 75 ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 14-2: 44-lead thin quad flat pack (tqfp) sst package code: tqj note: 1. complies with jedec publication 95 ms-026 acb dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (0.05) mm. 4. package body dimensions do not include mold flash. maximum allowable mold flash is .25mm. 44-tqfp-tqj-7 .45 .75 10.00 0.10 12.00 0.25 1.00 ref 0- 7 1 11 33 23 12 22 44 34 1.2 max. .95 1.05 .05 .15 pin #1 identifier .30 .45 .09 .20 .80 bsc 12.00 0.25 10.00 0.10 1mm
76 preliminary specification flashflex mcu sst89c58rc ?2008 silicon storage technology, inc. s71323-03-000 07/08 figure 14-3: 40-contact very-very-thin quad flat no-lead (wqfn) sst package code: qi note: 1. complies with jedec jep95 mo-220i, variant wjjd-5 except external paddle nominal dimensions. 2. from the bottom view, the pin #1 indicator may be either a 45-degree chamfer or a half-circle notch. 3. the external paddle is electrically connected to the die back-side and possibly to certain v ss leads. this paddle should be soldered to the pc board; it is suggested to connect this paddle to the v ss of the unit. connection of this paddle to any other voltage potential will result in shorts and/or electrical malfunction of the device. 4. untoleranced dimensions are nominal target dimensions. 5. all linear dimensions are in millimeters (max/min). 40-wqfn-6x6-qi-1 4.1 0.5 bsc see notes 2 and 3 pin #1 0.30 0.18 0.075 4.1 0.2 6.00 0.10 6.00 0.10 0.05 max 0.45 0.35 0.80 0.70 pin #1 top view bottom view side view 1mm
preliminary specification flashflex mcu sst89c58rc 77 ?2008 silicon storage technology, inc. s71323-03-000 07/08 table 14-1: revision history number description date 00 ? initial release of data sheet may 2007 01 ? added qif non-pb (f) ordering info ? edited product description ? fixed typo in figure 2-1, edited table 2-1 ? text changes on page 11 and text changes to figure 3-1 ? changes to tables 3-2, 3-3, 3-4, 3-5 and 3-7 ? removed note on page 20 and changed reset value ? changes to registers on pages 21-29 ? text changes on page 33 to section 4.2, table 4-2, and intable 4-3 ? edited sections 4.3, 4.3.1 and figure 4-8 ? edited figure 6-4. edited tables 6-3, 6-4, 6-5. ? edits in amsr on page 64 ? edited intable 12-6 and 12-7 and figure 12-10 ? changed vih4 parameter on page 66 aug 2007 02 ? removed ?fast mode? from product description ? edited description for p0[7:0], p1[7:0 ], p2[7:0], psen#, rst, ea#, and ale/ prog# in pin description table 2-1 ? replaced body text section 6.3.1, ?scl low timeout? ? edited body text section 6.3.2, ?scl high (smbus free) timeout? ? edited body text section 6.4, ?smbus sfr? ? replaced body text section 6.4.1, ?smbus control register? ? changed number of 8-bit status codes from 28 to 31 in two places section 6.4.4, ?status register? ? replaced globally: s1sta by sm0sta; s1dat by sm0dat; s1con by sm0con; s1adr by sm0adr; sio1 by smbus ? edited body text section 6.4.5, ?smbus scl high and low duty? ? edited title and footnotes for table 6-7 ? edited i il and i dd values in table 12-6 ? edited max parameters and footnote in table 12-9 feb 2008 03 ? changed prog-boot-default to prog-boot-from-user-vector, page 20 ? changed the value of boot-from-user-vector from ?1? to ?0?, figure 4-8, page 37. jul 2008 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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